Offset modeling in verilogA

Dear QilongNL,

QilongNL said:

However, from the forum I learned that the commands below

@initial_step begin

a=$random(seed) //seed is the sweep variable

end

does not work since $random only gives a pseudo-random number.

A few comments if I may followed by a couple of suggestions....

1. Why are you calling the $random() function in an iniital_step event? Most code I have see set the seed in the initial_step event to a variable and then call the relevant number generation function.

2. If a is intended to be a variable denoting the offset voltage of a comparator, why are you using the $random(0 function which produces a a signed integer, 32-bit pseudorandom number. I would think you might use either $rdist_normal which produces a real number?

3. If you are modeling the variation in the offset voltage of a comparator, I am wondering why you are concerned with the resulting output of the distribution being pseudo-random in lieu of truly random. A pseudorandom sequence can appear very random. As an example, Figure 1 compares the distributions of the output of a uniform and gaussian random number generator I use to model resistor value variation. In this example, the range was set to 20 ohms for the uniform distribution and the sigma set to 20 ohms for the normal distribution. For the purpose of modeling comparator offset voltage variaiton, I would think the resulting gaussian distribution might be sufficient.

Figure 1

4. If you want to use a verilog-A based generator, you might create a pseudorandom normal distribution manually using the outputs from two calls to a random uniform distribution where you provide the seed to one of them as your design variable. I think you could then use your desired sequence of seed values of [1,2...,100]. A specific algorithm to do this is the polar form of the Box-Muller transformation and dates to 1958. I used this algorithm in this manner to illustrate the resulting distribution of 100 sample of with with an increasing seed from 1 to 100 and the resulting distribution for a zero mean, sigma = 1 normal distribution is shown on page 1 of the attached file. You may compare it to using a single seed value of 1 and creating 100 samples of the same zero-mean sigma = 1 normal distribution on page 2.

5. A second suggestion is to change your design variable to the actual offset voltage. It may be an input to your verilog-A comparator. I recently wrote a script to create a set or corners that vary a design variable using a uniform or gaussian distrbuted value of the design variable. It will automatically create the corner file in a comma-separated variable file that you can directly import into Assembler. In this fashion, the sweep is already populated with the values of offset voltage and your verilog-A block will read the design variable assigned to the offset voltage for each corner. I documented it and placed a compressed file with example files and instructions in the Forum post at URL:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/52456/how-to-use-the-random-function-in-schematic

I hope these thoughts spur some ideas QilongNL.

Shawn

comparre_distrbutions_normal_single_seed_multiple_seeds_052423v1p0-compressed.pdf

I think the issue here is that changing the seed and then generating a single random number is not going to be very random (I did an experiment and it's not - there's a noticeable pattern to it - pretty much a straight line!). I suspect it may have been this post: https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/43062/verilog-random-seems-to-be-not-random that you were referring to as "However, from the forum"?

Anyway, one approach is loop through and make sure you retrieve the nth random number in the sequence. That's quick enough in an initial block, although not sure you'd want to do it with arbitrarily high "seed" value (a misnomer here; it's the sequence number you're changing):

module genrandom;

parameter integer seed=1;

integer iseed;
real a;
integer i;
analog begin
  @(initial_step) begin
//      iseed=seed;
//     $strobe(iseed);
      for(i=0; i<seed; i++) begin
// note - can remove the %1000 bit - this was just me constraining the values
// a bit.
	  a=$random()%1000;
      end
      $strobe("OUT:",seed,a);
  end
end

endmodule

I tested this with 50,000 values of "seed" (aka "sequence") and plotted a histogram of the results - with 50 bins, all were between 940 and 1070 - so fairly uniform.

Andrew.