Using PLL+Pnoise to simulate PLL, failed to converge

Dear Yongqi Hu,

Yongqi Hu said:

I am simulating the PLL (accomplished by Verilog A) using PLL+Pnoise, but it failed to converge, and I tried a lot of methods to make it converge, unfortunately, it all failed.

So I want to know if there are any methods to make the PLL converge.

Unfortunately, I do not know anywhere near enough information to provide any concrete suggestions (such as basic PLL architecture, divider(s), verilog-A modules, simulator (spectre, +aps, ++aps, spectre X?), version and simulator settings.

I am not sure if you saw the following recent Forum post concerning the use of pnoise for a PLL:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/55593/observing-pll-phase-noise-with-hbnoise/1388552#1388552

There may be some suggestions and documentation you may find relevant. There are many other discussions on the use of pnoise for PLL contained within the Forum.

Shawn

Dear Shawn,

I am sorry I forgot providing more specific information.

The PLL architecture is a simple Type I PLL, including XOR module, LPF module, VCO module(sinwave function), comparator module(convert sinwave to squre wave), divider(dividing ratio is 2), all these modules are verilog-A modules except for LPF module.

Simulator is ++ aps, the version is  20.1.0.534.isr17.

And I saw the Forum post you provided, the suggestions that provided were using trans simulation to simulate the phase noise of PLL, but the simulation time was too long, and I still want to use PSS+Pnoise to simulate pll, so could you please give some advice about it?

Thanks for your reply

Yongqi 

Yongqi,

There's still not really enough information to give you much advice on this - seeing the Spectre log file might help, but the best thing would be to contact customer support and sharing the test case so that an application engineer can take a look. In particular, it will be important to check that the Verilog-A models are truly not dependent upon hidden states (in other words, you've not just added the attributes to the model to suppress the hidden state check). There's specific steps you need to do to write a divider model that is hidden-state free - can you at least share that model here?

Andrew

Hi Andrew,

Sure, the following code is my divider verilog-A code. Actually, I change the divider veriloga-A model to a D-filp flop based divider, the PLL still didnot converge.

module divider(vin, vout);
input vin;
output vout;
electrical vin, vout;

integer cnt;
integer vout_val;

analog begin
@(initial_step) begin
cnt = 0 ;
end

@( cross( V(vin)-0.5, +1 ) ) begin
cnt = cnt+1 ;
if(cnt == 8)begin
cnt = 0;
end
end
end

analog begin
if(cnt == 0 |cnt == 1 |cnt == 2 |cnt == 3)begin
vout_val = 1;
end else begin
vout_val = 0;
end
end

analog begin
V( vout ) <+ transition( vout_val, 0, 10f ) ;

end

endmodule

Thanks for your reply

Yongqi

Yongqi,

This doesn't make sense. You said your divider was a divide by 2 - that model is a divide by 8. Secondly, there's no chance of that "failing to converge" in PSS. It simply won't run in PSS, because it contains hidden states. Spectre will report:

Error found by spectre during periodic steady state analysis `pss'.
    ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module
        components with hidden states found in component 'divider'. Skipped.

        forum171.va, declared in line 9: Hidden state variable: cnt

        Rewrite the module to remove the hidden state or if you confirm this
        hidden state will not affect the simulation result, you can ignore
        those hidden states in RF analysis by adding attribute
        'ignore_hidden_state' before the module declaration. For example, (*
        ignore_hidden_state *) module moduleA.

The suggested workaround of using (* ignore_hidden_state *) is not a solution here because the hidden state will affect the simulation result.

You're not going to get much help if in addition to not providing enough information you are not describing either the data you're using or the error you're seeing.

Andrew

Andrew,

I am sorry, I revised the verilog-A code to divider by-2 and the previous code is the unrevised version(which is divide by 8 ), and the following is the code

module divider(vin, vout);
input vin;
output vout;
electrical vin, vout;

integer cnt;
integer vout_val;

analog begin
@(initial_step) begin
cnt = 0 ;
end

@( cross( V(vin)-0.5, +1 ) ) begin
cnt = cnt+1 ;
if(cnt == 2)begin
cnt = 0;
end
end
end

analog begin
if(cnt == 0 )begin
vout_val = 1;
end else begin
vout_val = 0;
end
end

analog begin
V( vout ) <+ transition( vout_val, 0, 10f ) ;

end

endmodule

Thanks 

Yongqi

Yongqi,

It still has a hidden state though, so will fail in exactly the same way - i.e. with an error, not a convergence problem.

Andrew

Andrew,

But I didn't fail in the same way as you,  I'm either having issues with not converging, or the PSS keeps running, running and running.

And I tried to replace the divider to a transistor-based divider, it still failed to converge.

Yongqi

Have you added that attribute to your model? You didn't include the entire model because the `include "disciplines.vams" was missing - so maybe there was something above. Also, are you using Spectre?

Andrew

Yes, I have added that attribute to my model. And I am using spectre. The following picture is the error.

Well, that's not going to work (as I said before). The hidden state detection is there for a reason - the only time it's OK to add that attribute is when the hidden state does not affect the model (for example, it's related to printing some information, or it's in a signal source, or in an output measurement block). In this case this impacts the behaviour between input and output of the divider - see Hidden State in SpectreRF

Given that there may be other issues in your design or other models, please contact customer support (submit a case after logging in) - it's not going to be efficient to keep going back and forth trying to tease out or guess what you have done.

Andrew

Well, that's not going to work (as I said before). The hidden state detection is there for a reason - the only time it's OK to add that attribute is when the hidden state does not affect the model (for example, it's related to printing some information, or it's in a signal source, or in an output measurement block). In this case this impacts the behaviour between input and output of the divider - see Hidden State in SpectreRF

Given that there may be other issues in your design or other models, please contact customer support (submit a case after logging in) - it's not going to be efficient to keep going back and forth trying to tease out or guess what you have done.

Andrew