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Using PLL+Pnoise to simulate PLL, failed to converge

Yongqi Hu

I am simulating the PLL (accomplished by Verilog A) using PLL+Pnoise, but it failed to converge, and I tried a lot of methods to make it converge, unfortunately, it all failed.

So I want to know if there are any methods to make the PLL converge.

I really hope someone can give me some advice.

Thanks a lot.

  • Andrew Beckett
    in reply to Yongqi Hu

    Well, that's not going to work (as I said before). The hidden state detection is there for a reason - the only time it's OK to add that attribute is when the hidden state does not affect the model (for example, it's related to printing some information, or it's in a signal source, or in an output measurement block). In this case this impacts the behaviour between input and output of the divider - see Hidden State in SpectreRF

    Given that there may be other issues in your design or other models, please contact customer support (submit a case after logging in) - it's not going to be efficient to keep going back and forth trying to tease out or guess what you have done.

    Andrew

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