How to Implement Customized Pulse Voltage Source with Varying Frequencies in Cadence?

Dear Tod,

Tod said:

Is there any other way I can do to get the aforementioned Vref in Cadence, or do I need to write the behavorial model for it? If so, can anyone give me an example of how to write that behavorial Verilog code?

There are a several ways that come to mind that might be helpful to you. Please allow me to make a few comments prior to the suggestions.

1. I assume your goal is to study the transient response of the PLL under study as it undergoes a frequency step. As such, are you attempting to vary the frequency of your input reference clock as its frequency changes from 100 MHz to 150 MHz or from 150 MHz to 200 MHz? In other words, is there a defined df/dt (frequency ramp?) to use for the frequency transition or does the frequency change over one period of your input reference clock. The rate of change of the input reference clock frequency may impact the response of your PLL depending on its bandwidth and the design of its phase detector.

2. You also did not specify any other parameters of your reference clock source. Is it required to have a specific set of transitions times (i..e., rise and fall times) or duty cycle? Is the reference clock output waveform desired to be a piecewise linear signal or is it desired to include some type of bandwidth limiting?

3. Should your reference clock source contain any phase noise? If you are just studying the transient response of the PLL, this may not be necessary. However, it is something to consider as your PLL design progresses.

Suggestions

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a. In lieu of using a pulse source, it might be worth considering the use of a behavioral VCO  and a simple vpulse generator from the analogLIb to provide your reference clock.  In this fashion, the vpulse source generates the control voltage that changes between values that correspond to a frequency of 100 MHz, 150 MHz and 200 MHz at the simulation times of 0 - 100 ns, 100ns+ - 250 ns, and 250 ns+. For the VCO, Mr. Ken Kundert has written a verilog-A model for a VCO named vco1(out,in) that generates a square wave at:

I've attached a text file from his site of the model. I have to include the extension ".txt" to upload the file, but it should be removed when using the file such that it has the ".va" extension.

There are various parameters for his model that you can set to customize it for your application. Simply create a symbol view for the model with the inputs and outputs as defined in the model and create a behavioral view of the cell using its code. Call the symbol view in your test bench and set its control voltage input pin "in" to the output of your vpulse source that generates its control voltage.

b. A second suggestion is to create a custom pulse generator in verilog-A. It sounds as if this may not be something you are comfortable with doing. There are many excellent references on verilog-A including those on the Cadence on-line support portal that may be helpful. You might also use some of the code from the behavioral library (ahdl) as examples to get you started.

c. A third suggestion is to use a vpwlf  (piecewise linear source using file) source from the analogLib library and use a file to define its output voltage versus time characteristic. The location of the file to use is specified in the GUI for a vpwlf source. I have a custom C program that creates a piecewise linear square wave of arbitrary frequency and various forms of modulation with assignable transition times, duty cycle, modulation types and bandwidths. In its simplest use case, it can create a file of square wave samples of a given frequency. I assembled your desired waveform using it and have attached a pdf document that details its outputs with expanded views of the frequency transition regions and have attached it. Note, I had to change your transition time from 150 MHz to 200 MHz from 250 ns to just over 253 ns. This was necessary or your waveform will undergo a significant discontinuity. The compressed version of the file is too large to post. Hence, it is at

if you want to give it a try or simply view it in spectre using ViVA or simulate it as an input to a vpwlf source. I am unable to post the link as text as the spam filter will quarantine my message. However, if you type the first few characters (through the /u/), you may append them with the following text: s!AnM-GsAEZPoSrzxSfCjFZUIZMEQK?e=8xCbmo.

I hope this is useful to you Tod.

Shawn

0407.square_wave_100meg_100ns_150meg_253ns_200meg_1u_102423_documentation.pdf

Dear Tod,

I realized I did not include the copy of the vco1() module written by Mr. Ken Kundert. It is attached below - sorry!

Shawn

// Reference https://designers-guide.org/verilog-ams/functional-blocks/vco/vco.va
//
// Voltage controlled oscillator
// output is square wave with no jitter
//

module vco1 (out, in);

input in; voltage in;                           // input terminal
output out; voltage out;                        // output terminal
parameter real vmin=0;                          // input voltage that corresponds to minimum output frequency
parameter real vmax=vmin+1 from (vmin:inf);     // input voltage that corresponds to maximum output frequency
parameter real fmin=1 from (0:inf);             // minimum output frequency
parameter real fmax=2*fmin from (fmin:inf);     // maximum output frequency
parameter real vl=-1;                           // high output voltage
parameter real vh=1;                            // low output voltage
parameter real tt=0.01/fmax from (0:inf);       // output transition time
parameter real ttol=1u/fmax from (0:0.1/fmax);  // time tolerance
real freq, phase;
integer n;

analog begin
    // compute the freq from the input voltage
    freq = (V(in) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;

    // bound the frequency (this is optional)
    if (freq > fmax) freq = fmax;
    if (freq < fmin) freq = fmin;

    // bound the time step to assure no cycles are skipped
    $bound_step(0.6/freq);

    // phase is the integral of the freq modulo 2 pi
    phase = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);

    // identify the point where switching occurs
    @(cross(phase + `M_PI/2, +1, ttol) or cross(phase - `M_PI/2, +1, ttol))
        n = (phase >= -`M_PI/2) && (phase < `M_PI/2);

    // generate the output
    V(out) <+ transition(n ? vh : vl, 0, tt);
end
endmodule

Thank you so much for the help Mr Shawn! I actaully learned quite a bit as I did not expect that much answer.

ShawnLogan said:

2. You also did not specify any other parameters of your reference clock source. Is it required to have a specific set of transitions times (i..e., rise and fall times) or duty cycle? Is the reference clock output waveform desired to be a piecewise linear signal or is it desired to include some type of bandwidth limiting?

I was just giving an example, as I am able to observe lock for my current PLL design with a reference pulse votlage with 100MHz in frequency, 50% duty cycle, 0 to 1.8V as I'm using 180nm TN. From your response, I think the best option for my case is to still use a custom pulse generator using behavorial model, and I should learn some behavorial coding in Verilog in the future.

ShawnLogan said:

3. Should your reference clock source contain any phase noise? If you are just studying the transient response of the PLL, this may not be necessary. However, it is something to consider as your PLL design progresses.

Yes, currently I'm just observing the transient response, plotting Vcontrol vs time, and feedback frequency vs time to observe lock. I think moving forward, I will try to include some phase noise in the reference clk and do noise analysis and maybe improve my PLL topology.

Dear Tod,

Tod said:

From your response, I think the best option for my case is to still use a custom pulse generator using behavorial model, and I should learn some behavorial coding in Verilog in the future.

Sounds good. If you want access by any chance to the program I use to create a custom piecewise linear file with various modulation options, let me know. Otherwise, good luck!

Tod said:

I think moving forward, I will try to include some phase noise in the reference clk and do noise analysis and maybe improve my PLL topology.

This sounds like a reasonable approach as you will then have greater confidence in the basic operation and characteristics of your PLL under study.

Shawn