AMS simulation IE settings

Dear paulinho,

paulinho said:

Is the issue of toggling twice related to the IE set up or am I missing something else ?

I am not the right one to ask about an IE setup, but there are several thoughts I had after reading your question and viewing your waveform. They may or may not be relevant, so please excuse my comments if they are!

1. A T flip-flop's output state is determined by both its clock input and its T input. You are only displaying the clock input and the "q" output. What is the T input signal over the time interval of your plot?

2. Some T flip-flops have a reset (sync or sync). If this one does, what is the reset signal over the time interval of your plot?

3. You are also using a behavioral T-flip flip - which I assume is in verilog. Have you verified this functional block or is this the attempt to verify it? In essence, are you sure the coding is correct?

4. With a 100 kHz clock frequency, you mentioned the rise time is 10% of the period. However, from your plot it appears the rise time is 500 ns - which is 5% of the 100 kHz period and has a slope of 800 mV/500 ns = 1.6e6 V/sec or 1.6 V/us - which is incredibly slow. I am concerned that the reason you are seeing more than a single transition is that the T flip-flop is remaining in its high gain state too long as its input clock remains near the switching threshold for a extended period of time. Therefore, it effectively acts as an oscillator until the input clock reaches a voltage that sufficiently exceeds its input switching threshold. An easy way to test this is to either reduce the rise and fall times to something much, much less than 5% of the 100 kHz period or, alternately, operate the clock at a much higher frequency (>> 100 kHz). In both cases, the time the clock remains near its input switching threshold will be much less and its propagation delay time will likely be great enough to avoid multiple output switch events (i,e., an oscillation).

Shawn

You really need to provide more information - such as the other inputs to the flip-flop and ideally the Verilog code for the flip-flop (maybe a simple test bench including just a single instance of the flip-flop to check it out would be a good idea). Looking at one analog input and one digital output without any sight of the rest of the circuit is not going to get very far.

Andrew

Thanks Andrew & Shawn for looking into it. Below shown is the verilog code and Testbench for it.

If i understand correctly, the clk_transition attribute usually specified in .lib files is around 10-20% of the time period. Thats why I gave a rise/fall time of 10%. I also tried with 5% and still doesnt make a difference. 

OK, the issue is that the default rise time in the ie card is 0.2ns, whereas your rise time is over 1000 times that (0.5us from the screenshot). I ran your test case (with a rise time of 1/fs/10) and if I run with the interactive debugger (simVision) and look at the clk inside the tff module, you can see:

Because the rise time is so slow, it spends too long in transition and so the interface element is outputting an unknown for a period of time. You're getting two posedge events as a result - once as it goes from 0 to unknown, and another when going from unknown to 1. 

If you go to the IE setup and then check the Advanced Setup and increase the tr value:

then you get more sensible results (because now the transition is within the expected range of the interface element (connect module) and so it won't go to X in the middle of the transition:

Hope that helps!

Andrew

Hi Andrew,

Thanks. That works