AMS simulation IE settings

Dear paulinho,

paulinho said:

Is the issue of toggling twice related to the IE set up or am I missing something else ?

I am not the right one to ask about an IE setup, but there are several thoughts I had after reading your question and viewing your waveform. They may or may not be relevant, so please excuse my comments if they are!

1. A T flip-flop's output state is determined by both its clock input and its T input. You are only displaying the clock input and the "q" output. What is the T input signal over the time interval of your plot?

2. Some T flip-flops have a reset (sync or sync). If this one does, what is the reset signal over the time interval of your plot?

3. You are also using a behavioral T-flip flip - which I assume is in verilog. Have you verified this functional block or is this the attempt to verify it? In essence, are you sure the coding is correct?

4. With a 100 kHz clock frequency, you mentioned the rise time is 10% of the period. However, from your plot it appears the rise time is 500 ns - which is 5% of the 100 kHz period and has a slope of 800 mV/500 ns = 1.6e6 V/sec or 1.6 V/us - which is incredibly slow. I am concerned that the reason you are seeing more than a single transition is that the T flip-flop is remaining in its high gain state too long as its input clock remains near the switching threshold for a extended period of time. Therefore, it effectively acts as an oscillator until the input clock reaches a voltage that sufficiently exceeds its input switching threshold. An easy way to test this is to either reduce the rise and fall times to something much, much less than 5% of the 100 kHz period or, alternately, operate the clock at a much higher frequency (>> 100 kHz). In both cases, the time the clock remains near its input switching threshold will be much less and its propagation delay time will likely be great enough to avoid multiple output switch events (i,e., an oscillation).

Shawn

Dear paulinho,

paulinho said:

Is the issue of toggling twice related to the IE set up or am I missing something else ?

I am not the right one to ask about an IE setup, but there are several thoughts I had after reading your question and viewing your waveform. They may or may not be relevant, so please excuse my comments if they are!

1. A T flip-flop's output state is determined by both its clock input and its T input. You are only displaying the clock input and the "q" output. What is the T input signal over the time interval of your plot?

2. Some T flip-flops have a reset (sync or sync). If this one does, what is the reset signal over the time interval of your plot?

3. You are also using a behavioral T-flip flip - which I assume is in verilog. Have you verified this functional block or is this the attempt to verify it? In essence, are you sure the coding is correct?

4. With a 100 kHz clock frequency, you mentioned the rise time is 10% of the period. However, from your plot it appears the rise time is 500 ns - which is 5% of the 100 kHz period and has a slope of 800 mV/500 ns = 1.6e6 V/sec or 1.6 V/us - which is incredibly slow. I am concerned that the reason you are seeing more than a single transition is that the T flip-flop is remaining in its high gain state too long as its input clock remains near the switching threshold for a extended period of time. Therefore, it effectively acts as an oscillator until the input clock reaches a voltage that sufficiently exceeds its input switching threshold. An easy way to test this is to either reduce the rise and fall times to something much, much less than 5% of the 100 kHz period or, alternately, operate the clock at a much higher frequency (>> 100 kHz). In both cases, the time the clock remains near its input switching threshold will be much less and its propagation delay time will likely be great enough to avoid multiple output switch events (i,e., an oscillation).

Shawn