Virtuoso AMS error

Can you share the Verilog-AMS code?

Also, the XCELIUM and IC versions that you are using.

Andrew 

Here is my Verilog-AMS code.
sttmram0_32_16.txt

Here is my Verilog-AMS code.
sttmram0_32_16.txt

You'll need to contact customer support. It appears that the code compiles OK, but the option used to extract some of the structure information (the xmvlog -zparse option) is failing with an internal error. That needs investigating by R&D. Please log into the support site and then submit a case together with the model code you provided here.

Regards,

Andrew

OK, thanks.

Emily,

As a stop-gap, you can comment out (with /* and */ ) the contents of the module - leave all the I/O definitions. You also need to comment out (with //) the two parameter real array lines (Rap and Rp); these are the two that seem to be causing the problem with the analysis. Save and Extract, and then remove the comments. At least this way you'll end up with the netlist.oa (and will be prompted for symbol creation), and then having removed the comments it would fail to extract, but you'd still have the previous extraction.

I had initially thought of suggesting you replacing the core of the module with loops with genvars to create the structure, but I think the real issue is the big parameter array.

For support (your point about support access seems to have been deleted from the thread), if you're an academic institution then you would either go via Europractice support (if in the Europractice scheme) or elsewhere you can get your University liaison (whoever is responsible for the University program at your institution) to create the support case - it's just not open to everyone so that there is some level of filtering within each institution.

Regards,

Andrew

Copy that, I'll give it another shot with a different approach, thank you very much!

Best Regards,

Emily