Community Mixed-Signal Design xmelab: *E,CUVHNF error using Xcelium 19.09-s008

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xmelab: *E,CUVHNF error using Xcelium 19.09-s008

markris

Hello everyone,

I have the following error starting a simulation with Xcelium 19.09-s008:

xmelab: *E,CUVHNF (netlist.vams,3630|51): Hierarchical name component lookup failed at 'round'.

Looking at the netlist, exactly at the line 3630, I get that a device parameter is using the "round" function that is correctly solved using Spectre stand alone instead:

nmos_test #(.mult(round(20/2-0.5)),

I guess the issue is related to the fact that the netlist in AMS designer is based on VAMS language it supports only "floor" and not "round" as a rounding function (but the rounding behavior will change obviously). 

However, is there a way cia e a switch in xrunArgs to solve this issue and get the function solved in Xcelium too without changing the design?

Thanks a lot in advance!

Parents

  • Hi Marco,

    In fact I wasn't aware that Spectre supported round - I then found that this was added via CCR 1668374 in an MMSIM15.1/SPECTRE16.1 hotfix a number of years back (although I don't think it's documented - it probably should be). I haven't found any reports of the specific issue with AMS Designer (I can reproduce the issue). As you say, round() is not in the Verilog-AMS standard.

    What's odd here is that the subtraction of 0.5 means that round(N-0.5) is the same as doing floor(N) (other than with negative numbers), so maybe the solution is best to change the expression to use floor()?

    Otherwise I think it would need an enhancement for AMS to support this non-standard function. I did consider defining an analog function to implement round, but you can't use an analog function in this context.

    Andrew

Reply

  • Hi Marco,

    In fact I wasn't aware that Spectre supported round - I then found that this was added via CCR 1668374 in an MMSIM15.1/SPECTRE16.1 hotfix a number of years back (although I don't think it's documented - it probably should be). I haven't found any reports of the specific issue with AMS Designer (I can reproduce the issue). As you say, round() is not in the Verilog-AMS standard.

    What's odd here is that the subtraction of 0.5 means that round(N-0.5) is the same as doing floor(N) (other than with negative numbers), so maybe the solution is best to change the expression to use floor()?

    Otherwise I think it would need an enhancement for AMS to support this non-standard function. I did consider defining an analog function to implement round, but you can't use an analog function in this context.

    Andrew

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