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PSS + PNOISE Simulation Problem for the PLL

Hi all,

My PSS analysis is not converging and giving errors. I have attached the images for settings of my PSS analysis. Cannot figure where I am getting wrong. My beat frequency is 86.25 Mhz and PLL is locking at 690Mhz. It's a basic CP-PLL.

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Andrew Beckett over 1 year ago

I'm assuming your reference clock is 86.25MHz and you have a divide-by-8 in the PLL loop? Your VCO output frequency seems to be wandering quite a bit - do you have a dead band in your phase detector?

It's probably easiest to deal with this through customer support (submit a support case after logging in), to be honest, as seeing your design/setup would make it easier to debug.

Andrew
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MtnDew12fl over 1 year ago in reply to Andrew Beckett

First Question is Yes. And for second, I think that I do have a dead band problem. Thank You for pointing that out.
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MtnDew12fl over 1 year ago in reply to Andrew Beckett

First Question is Yes. And for second, I think that I do have a dead band problem. Thank You for pointing that out.
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