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Why my Verilog‘s digital outputs are correct in Vivado but 'x' in Cadence AMS?

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Here is what it should be:

but this is the same Verilog in AMS, i`m wondering how to make the output right:

This is the tb schematic:

And here`s the Verilog code, it described a state machine:

I can make right with another Verilog code and the same process, so is there something wrong in my code?

Here is the another one, is a logic gate.

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  • in reply to tpylant

    Are you talking about the final image?  I am designing a sequencing circuit based on SRAM In-Memory-Computing. And the final image is a simulation of a compare circuit, which is used to compare the data in two selected storage unit(2bit) and signal "exchange".

     The circuits I'm designing are used to verify the correctness of my SRAM， I don't need to think about their performance for now,  as long as they function correctly

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