White phase noise in VCO decays with frequency – not flat as expected

Hi everyone,

I’m implementing a simple sinusoidal VCO in Verilog-A for phase noise analysis using PSS+PNOISE. I added white phase noise using only the white_noise function, as shown in the code snippet below. I expect the noise floor to remain flat (constant) at higher frequency offsets, but instead, it decays approximately at 20 dB/dec until it reaches the expected bottom value.

Verilog-A snippet:

`include "disciplines.vams"
`include "constants.vams"

module vco0 ( vctrl, out );

input vctrl; voltage vctrl;
output out; voltage out;
parameter real vmin=0;
parameter real vmax=vmin+1 from (vmin:inf);
parameter real fmin=1 from (0:inf);
parameter real fmax=2*fmin from (fmin:inf);

parameter real bottom = -130;
real wn_level = pow(10, bottom/10);

real freq, phase;
integer n;

real wn;

analog begin
 freq = (V(vctrl) - vmin)*(fmax - fmin) / (vmax - vmin) + fmin;

 if (freq > fmax) freq = fmax;
 if (freq < fmin) freq = fmin;

 phase = 2*`M_PI*idtmod(freq, 0, 1, -0.5);

 wn = white_noise(wn_level, "vco_white");

 V(out) <+ sin(phase + wn);
end
endmodule

I’m attaching a plot from my PNOISE simulation where you can see this behavior. I’ve also included a reference line with a 20 dB/dec slope to highlight that the noise curve follows that same decline before reaching the bottom at -130 dBc/Hz. This seems to contradict the assumption that white phase noise should produce a flat region in the phase noise spectrum.

I also attached the configuration of my PSS and PNOISE simulation, as well as the testbench I'm using to this simulations.

Link for the files (images for configurations and responses): https://drive.google.com/drive/folders/1t1UDG6E_qu5o_2h0W1WK1M_lZ9LUtvHN?usp=sharing

Why is the white phase noise not flat as expected?

Any insights would be greatly appreciated. Thanks in advance!

Best regards,
Bruno.