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Including variables from a fil

AA202510057331 3 days ago

Hi,

I am using

IC25.1,

Spectre 24.1.0.288.isr5

Xcelium 25.03

I am trying to include variables from an external file so that they are recognized and used in my simulation, along with the other variables defined in the Maestro view GUI.

If it were a fully continuous-time simulation using just one of Spectre engines (APS, X, ..., etc), I can easily do that by putting my variables in a file "my_vars.scs" and including them in my model libraries.

However, when I want to do something similar in an AMS environment (where a cds_globals.vams is auto-created and populated with variables from the maestro view), the variables in "my_vars.scs" are not recognized during the initial "netlisting" and thus cause an error.

How/Where can I include a file with those variables, so that they are recognized during netlisting?

Or is there a way to alter the way "cds_globals.vams" file is generated so that it could auto-include a file containing the variables -after the "cds_globals" module header- from the external file and pass them along with all other GUI-defined variables?

Things I tried:

I tried copying the generated "cds_globals.vams" file to be "cds_globals_mine.vams", and manually added an include statement to include "my_vars.vams" after the "cds_globals" module header. Then using an "hdl.var" file with

DEFINE XRUNOPTS /path_to_/cds_globals_mine.vams

It includes my variables but, the issue with that is that it doesn't update values if changes were made on the GUI anymore.

Parents

Saloni Chhabra 2 days ago

Hi,

It’ll help to see the exact netlisting error. If your design variable appears in Maestro view without a value (at the time of netlisting) and becomes the reason for netlisting error, you can choose to enter any dummy value for all such variables in Maestro view and let these be overridden by 'my_vars.scs' in Model Libraries.

An example .scs file :

simulator lang=spectre

options options redefinedparams=warning

// vdd was defined as 0 in Maestro

parameters vdd=2

Regards,

Saloni
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Saloni Chhabra 2 days ago

Hi,

It’ll help to see the exact netlisting error. If your design variable appears in Maestro view without a value (at the time of netlisting) and becomes the reason for netlisting error, you can choose to enter any dummy value for all such variables in Maestro view and let these be overridden by 'my_vars.scs' in Model Libraries.

An example .scs file :

simulator lang=spectre

options options redefinedparams=warning

// vdd was defined as 0 in Maestro

parameters vdd=2

Regards,

Saloni
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AA202510057331 2 days ago in reply to Saloni Chhabra

Hi Saloni,

Thanks for your reply.

I created a full, simplified testcase with the two scenarios. Both simulate a simple VerilogA module that just prints out the parameter values passed to it from the GUI at the initial_step transient event. It also outputs those as a voltage on its output nets.

The two variables I am passing are "test_val_gui" and "test_val_file" for verilogA parameters "test_val_gui" and "test_val_file" respectively. The "gui" one is supposed to be passed from the mastro view while the "file" one is supposed to be included via a file.

The verilog module testcase_veriloga is shown below

Fullscreen veriloga.txt Download

`include "constants.vams"
`include "disciplines.vams"

module testcase_veriloga(clk, out_gui, out_file);

input clk;
output out_gui, out_file;
electrical clk, out_gui, out_file;

parameter real test_var_gui = 0;
parameter real test_var_file = 0;

analog begin

@(initial_step) begin
$display("Testcase VerilogA %M: variable test_var_gui value passed is %f", test_var_gui);
$display("Testcase VerilogA %M: variable test_var_file value passed is %f", test_var_file);
end
V(out_gui) <+ transition(test_var_gui, 0, 1p, 1p);
V(out_file) <+ transition(test_var_file, 0, 1p, 1p);
end


endmodule

The testbench itself contains an instance of this module and a clock source just to make sure the engine is running. It runs a transient sim.

A. Spectre only scenario with my_vars.scs included in model libraries.

Include the file "my_vars.scs" (below) in the model_libraries section.
Set the spectre redefinedparams option to warning or ignore to avoid errors from variable "test_val_file" double definition (The one in the file and the unintended auto-imported one in the GUI)
Running the simulation and ignoring the unset variable warning (ASSEMBLER-1610), as we already know the definition in the file sets that variable
This case runs normally, and the variables are correctly passed to the VerilogA module as indicated by its output voltages and messages.

Log and netlist below

Fullscreen testcase_spectreonly_netlist.txt Download

// Point Netlist Generated on: Oct  6 10:21:05 2025
// Generated for: spectre
// Design Netlist Generated on: Oct  6 10:21:05 2025
// Design library name: testcases
// Design cell name: tb_testcase_ams_include_vars
// Design view name: config
simulator lang=spectre
include "ade_e.scs"
global 0
parameters test_val_file temperature=27 test_val_gui=10 clk_f=1G
include "/Project_Path/ProjectX/cadence/my_vars.scs"

// Library name: testcases
// Cell name: tb_testcase_ams_include_vars
// View name: schematic
// Inherited view list: spectre spice pspice verilog verilogams
// behavioral functional systemVerilog schematic veriloga vhdl vhdlams
// wreal
V0 (clk 0) vsource dc=1 type=pulse val0=0 val1=1 period=1/clk_f \
        delay=-(1p)/2 rise=1p fall=(1p) width=0.5*(1/clk_f-(1p)-((1p)))
I0 (clk out_gui out_file) testcase_veriloga test_var_gui=test_val_gui \
        test_var_file=test_val_file
simulatorOptions options psfversion="1.4.0" temp=27 tnom=27 scalem=1.0 \
    scale=1.0 gmin=1e-12 rforce=1 redefinedparams=warning maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=sqldb 
tran tran stop=3n write="spectre.ic" writefinal="spectre.fc" \
    annotate=status 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/Project_Path/ProjectX/cadence/testcases/testcase_veriloga/veriloga/veriloga.va"

Fullscreen testcase_spectreonly_log.txt Download

Spectre (R) Circuit Simulator
Version 24.1.0.288.isr5 64bit -- 3 Apr 2025
Copyright (C) 1989-2025 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: username   Host: hostname   HostID: D90AF471   PID: 4075422
Memory  available: 474.9463 GB  physical: 540.1019 GB
Linux   : Rocky Linux release 9.6 (Blue Onyx)
CPU Type: Intel(R) Xeon(R) Gold 5115 CPU @ 2.40GHz
        Socket: Processors [Frequency] (Hyperthreaded Processor)
        0:       0 [2799.8] ( 20 ),  2 [2800.2] ( 22 ),  4 [3200.0] ( 24 )
                 6 [3200.0] ( 26 ),  8 [2800.0] ( 28 ), 10 [2800.1] ( 30 )
                12 [3200.0] ( 32 ), 14 [2798.9] ( 34 ), 16 [2744.7] ( 36 )
                18 [3200.0] ( 38 )
        1:       1 [2800.0] ( 21 ),  3 [2800.1] ( 23 ),  5 [2800.0] ( 25 )
                 7 [2450.5] ( 27 ),  9 [2758.3] ( 29 ), 11 [2800.1] ( 31 )
                13 [2800.0] ( 33 ), 15 [2800.0] ( 35 ), 17 [2800.0] ( 37 )
                19 [2780.0] ( 39 )
        
System load averages (1min, 5min, 15min) : 221.9 %, 221.8 %, 223.4 %
Hyperthreading is enabled
HPC is enabled


Simulating `input.scs' on hostname at 10:21:07 AM, Mon Oct 6, 2025 (process id: 4075422).
Current working directory: /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/1/DLL_SAR_NEW_tb_testcase_ams_include_vars_1/netlist
Command line:
    /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/bin/spectre  \
        -64 input.scs +escchars +log ../psf/spectre.out -format psfxl  \
        -raw ../psf +preset=mx +mt +lqtimeout 900 -maxw 5 -maxn 5 -env  \
        ade  \
        +adespetkn=0001089D13A302B663E41FB550AF0DF415A679A322D5069144BF588C12F604E07EF416DC01A319B562BB63D30AA94CE045A374D82AFD2CB778D05DFA1ADC4F9259DE79D15D9175FF349871C618F215BB58EA77C714A91AE358F726822CD674D30EAE79D118F874D3349879D118F874D334981132E27A8E515C7B000036AA  \
        -ahdllibdir  \
        /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB  \
        +logstatus

Simulation Id: 83jaAALHXd9eImmF
Licensing Information:
[10:21:07.219994] Configured Lic search path (24.01-s002): 5280@linlic8.engr.oregonstate.edu:7188@linlic8.engr.oregonstate.edu

Licensing Information:
[10:21:08.089672] Periodic Lic check successful

Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libphilips_I_sh.so ...
Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file:  /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/1/DLL_SAR_NEW_tb_testcase_ams_include_vars_1/netlist/input.scs

Notice from spectre during circuit read-in.
    Pre_Configuration file used: /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/preset.precfg
    Configuration file used: `/usr/local/apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/preset.cfg'.

Reading link:  /usr/local/apps/cadence
Reading link:  /usr/local/apps
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/preset.precfg
Reading file:  /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/1/DLL_SAR_NEW_tb_testcase_ams_include_vars_1/netlist/ade_e.scs
Reading file:  /Project_Path/ProjectX/cadence/my_vars.scs
Reading file:  /Project_Path/ProjectX/cadence/testcases/testcase_veriloga/veriloga/veriloga.va
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/preset.cfg
Time for NDB Parsing: CPU = 281.367 ms, elapsed = 798.539 ms.
Time accumulated: CPU = 481.917 ms, elapsed = 798.541 ms.
Peak resident memory used = 196 Mbytes.


Warning from spectre during circuit read-in.
    WARNING (SFE-2297): "/Project_Path/ProjectX/cadence/my_vars.scs" 4: Parameter `test_val_file' is already defined in the same block, previous definition is ignored.

Created directory /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB/ (775)
Created directory /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB//603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/ (775)
Reading file:  /scratch/simulation/ProjectX/DLL_SAR_NEW/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.46/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB/603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_testcase_veriloga.so
Created directory /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB//603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/obj/optimize/5.0 
Copying files from directory /scratch/simulation/ProjectX/DLL_SAR_NEW/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.46/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB/603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/ to directory /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB//603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/
Finished copying files from /scratch/simulation/ProjectX/DLL_SAR_NEW/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.46/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB/603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/ to /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB//603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/.
The simulator has reused the existing Verilog-A libraries for this simulation run. If you do not want to use these libraries, set the 'CDS_AHDL_REUSE_LIB' environment variable to 'NO' and rerun the simulation.
Existing shared object for module testcase_veriloga is up to date.
Installed compiled interface for testcase_veriloga.
Time for Elaboration: CPU = 27.87 ms, elapsed = 184.978 ms.
Time accumulated: CPU = 509.898 ms, elapsed = 983.634 ms.
Peak resident memory used = 205 Mbytes.

 Start ADE Session ID: 83jaAALHXd9eImmF

Time for EDB Visiting: CPU = 4.492 ms, elapsed = 8.65388 ms.
Time accumulated: CPU = 514.567 ms, elapsed = 992.465 ms.
Peak resident memory used = 206 Mbytes.


Notice from spectre during initial setup.
    Ignorevaref=yes is ignored since all nodes are connected to Verilog-A modules.
Notice from spectre during topology check.
    Only one connection to the following 3 nodes:
        0
        out_gui
        out_file
Notice from spectre during initial setup.
    Multithreading is disabled due to the size of the design being too small.


Netlist title:
        // Point Netlist Generated on: Oct  6 10:21:05 2025


Global user options:
         psfversion = 1.4.0
               temp = 27
               gmin = 1e-12
             rforce = 1
           maxnotes = 5
           maxwarns = 5
             digits = 5
               cols = 80
             pivrel = 0.001
           sensfile = ../psf/sens.output
     checklimitdest = sqldb
               save = allpub
               tnom = 27
             scalem = 1
              scale = 1

Scoped user options:

Circuit inventory:
              nodes 3
  testcase_veriloga 1     
            vsource 1     

Analysis and control statement inventory:
               info 7     
               tran 1     

Output statements:
             .probe 0     
           .measure 0     
               save 0     

Design checks inventory:
          paramtest 1     


Notice from spectre during initial setup.
    Protected devices exist and are not included in the circuit inventory.
    Spectre X preset=mx enabled.

Time for parsing: CPU = 5.661 ms, elapsed = 8.35586 ms.
Time accumulated: CPU = 520.384 ms, elapsed = 1.00098 s.
Peak resident memory used = 210 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
   -   (Spectre X) Multi-threading. The recommended number of threads is 1, consider adding +mt=1 on command line.
~~~~~~~~~~~~~~~~~~~~~~

***********************************************
Transient Analysis `tran': time = (0 s -> 3 ns)
***********************************************
Testcase VerilogA I0: variable test_var_gui value passed is 10.000000
Testcase VerilogA I0: variable test_var_file value passed is 13.256000
Convergence achieved in 2 iterations.
DC simulation time: CPU = 833 us, elapsed = 838.041 us.

Opening the PSFXL file ../psf/tran.tran.tran ...
Important parameter values:
    start = 0 s
    outputstart = 0 s
    stop = 3 ns
    step = 3 ps
    maxstep = 60 ps
    ic = all
    useprevic = no
    skipdc = no
    reltol = 1e-03
    abstol(V) = 1 uV
    abstol(I) = 1 pA
    temp = 27 C
    tnom = 27 C
    tempeffects = all
    errpreset = moderate
    method = trap
    lteratio = 3.5
    relref = allglobal
    cmin = 0 F
    gmin = 1 pS
    rabsshort = 1 mOhm


Notice from spectre during transient analysis `tran'.
    Multithreading is disabled due to the size of the design being too small.


Output and IC/nodeset summary:
                 save   1       (current)
                 save   3       (voltage)

    tran: time = 123.5 ps    (4.12 %), step = 60 ps           (2 %)
    tran: time = 243.5 ps    (8.12 %), step = 60 ps           (2 %)
    tran: time = 423.5 ps    (14.1 %), step = 60 ps           (2 %)
    tran: time = 540.5 ps      (18 %), step = 38 ps        (1.27 %)
    tran: time = 720.5 ps      (24 %), step = 60 ps           (2 %)
    tran: time = 840.5 ps      (28 %), step = 60 ps           (2 %)
    tran: time = 999.5 ps    (33.3 %), step = 49.5 ps      (1.65 %)
    tran: time = 1.172 ns    (39.1 %), step = 60 ps           (2 %)
    tran: time = 1.292 ns    (43.1 %), step = 60 ps           (2 %)
    tran: time = 1.456 ns    (48.5 %), step = 43.75 ps     (1.46 %)
    tran: time = 1.606 ns    (53.5 %), step = 60 ps           (2 %)
    tran: time = 1.726 ns    (57.5 %), step = 60 ps           (2 %)
    tran: time = 1.906 ns    (63.5 %), step = 60 ps           (2 %)
    tran: time = 2.049 ns    (68.3 %), step = 46.62 ps     (1.55 %)
    tran: time = 2.229 ns    (74.3 %), step = 60 ps           (2 %)
    tran: time = 2.349 ns    (78.3 %), step = 60 ps           (2 %)
    tran: time = 2.499 ns    (83.3 %), step = 45.19 ps     (1.51 %)
    tran: time = 2.668 ns    (88.9 %), step = 60 ps           (2 %)
    tran: time = 2.788 ns    (92.9 %), step = 60 ps           (2 %)
    tran: time = 2.954 ns    (98.5 %), step = 45.91 ps     (1.53 %)
Number of accepted tran steps =             71

Maximum value achieved for any signal of each quantity: 
V: V(out_file) = 13.26 V
I: I(V0:p) = 0 A

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Post-Transient Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


During simulation, the CPU load for active processors is :
         0 (7.4 %)       1 (22.3 %)      2 (2.2 %)       3 (11.6 %)
         4 (2.2 %)       5 (4.3 %)       6 (2.1 %)       7 (8.4 %)
         8 (7.4 %)       9 (5.3 %)      10 (2.1 %)      11 (9.9 %)
        12 (8.7 %)      13 (6.3 %)      14 (4.2 %)      15 (3.2 %)
        16 (43.6 %)     17 (26.3 %)     18 (4.3 %)      19 (2.1 %)
        20 (6.5 %)      21 (3.2 %)      22 (2.2 %)      23 (26.6 %)
        24 (5.4 %)      25 (9.6 %)      26 (36.8 %)     27 (6.3 %)
        28 (75.0 %)     29 (21.1 %)     30 (2.1 %)      31 (20.7 %)
        32 (4.2 %)      33 (25.5 %)     34 (1.1 %)      35 (11.8 %)
        36 (2.2 %)      37 (2.1 %)      38 (34.8 %)     39 (3.2 %)
        Total: 484.3%
Initial condition solution time: CPU = 904 us, elapsed = 910.044 us.
Intrinsic tran analysis time:    CPU = 8.246 ms, elapsed = 8.6081 ms.
Total time required for tran analysis `tran': CPU = 12.168 ms, elapsed = 12.538 ms, util. = 97%.
Time accumulated: CPU = 559.597 ms, elapsed = 1.04084 s.
Peak resident memory used = 214 Mbytes.

finalTimeOP: writing operating point information to rawfile.

Opening the PSF file ../psf/finalTimeOP.info ...
modelParameter: writing model parameter values to rawfile.

Opening the PSF file ../psf/modelParameter.info ...
element: writing instance parameter values to rawfile.

Opening the PSF file ../psf/element.info ...
outputParameter: writing output parameter values to rawfile.

Opening the PSF file ../psf/outputParameter.info ...
designParamVals: writing netlist parameters to rawfile.

Opening the PSFASCII file ../psf/designParamVals.info ...
primitives: writing primitives to rawfile.

Opening the PSFASCII file ../psf/primitives.info.primitives ...
subckts: writing subcircuits to rawfile.

Opening the PSFASCII file ../psf/subckts.info.subckts ...
Licensing Information:
Lic Summary:
[10:21:08.292339] Cdslmd servers:5280@linlic8.engr.oregonstate.edu:7188@linlic8.engr.oregonstate.edu
[10:21:08.816683] Feature usage summary:
[10:21:08.816688] Virtuoso_Multi_mode_Simulation
[10:21:08.816689] Spectre_X_MMSIM_Lk


Aggregate audit (10:21:08 AM, Mon Oct 6, 2025):
Time used: CPU = 568 ms, elapsed = 1.05 s, util. = 54%.
Time spent in licensing: elapsed = 161 ms, percentage of total = 15.3%.
Peak memory used = 215 Mbytes.
Simulation started at: 10:21:07 AM, Mon Oct 6, 2025, ended at: 10:21:08 AM, Mon Oct 6, 2025, with elapsed time (wall clock): 1.05 s.
spectre completes with 0 errors, 1 warning, and 10 notices.

B. AMS scenario with my_vars.scs included in model libraries.

Include the file "my_vars.scs" (below) in the model_libraries section.
Set the spectre redefinedparams option to warning or ignore to avoid errors from variable "test_val_file" double definition (The one in the file and the unintended auto-imported one in the GUI)
Running the simulation and ignoring the unset variable warning (ASSEMBLER-1610), as we already know the definition in the file sets that variable
Deleting the empty "test_val_file" unset variable created before from the test "Design Variables" section. Not sure if this is necessary.
This case gives a sim error and upon checking it shows
xmelab: *E,CUVHNF (./netlist.vams,28|59): Hierarchical name component lookup failed at 'cds_globals.test_val_file'.

Log, netlist and cds_globals below

Fullscreen testcase_ams_netlist.txt Download

// AMS netlist generated by the AMS Unified netlister
// IC subversion:  IC25.1-64b.38 
// Xcelium version: 25.03-s005
// Copyright(C) 2005-2009, Cadence Design Systems, Inc
// User: username Pid: 3050583
// Design library name: testcases
// Design cell name: tb_testcase_ams_include_vars
// Design view name: config
// Solver: Spectre

`include "disciplines.vams"
`include "userDisciplines.vams"
// HDL file - testcases, testcase_veriloga, veriloga.
// Library - testcases, Cell - tb_testcase_ams_include_vars, View - schematic
// LAST TIME SAVED: Oct  6 10:19:47 2025
// NETLIST TIME: Oct  6 10:39:59 2025

`worklib testcases
`view schematic

`timescale 1ns / 1ns 
(* cds_ams_schematic *)

module tb_testcase_ams_include_vars ( );
wire clk;
wire out_gui;
wire out_file;
testcase_veriloga #(.test_var_file(cds_globals.test_val_file), .test_var_gui(cds_globals.test_val_gui)) I0 (.out_file( out_file ), .out_gui( out_gui ), .clk( clk ));
vsource #(.dc(1), .type("pulse"), .val0(0), .val1(1), .period(1/cds_globals.clk_f), .delay(-(1e-12)/2), .rise(1e-12), .fall(1e-12), .width(0.5*(1/cds_globals.clk_f-(1e-12)-((1e-12))))) V0 (clk, cds_globals.\gnd! );

endmodule
`noworklib
`noview

Fullscreen testcase_ams_cds_globals.txt Download

// Verilog-AMS cds_globals module for top-level cell:
//    testcases/tb_testcase_ams_include_vars.
// Generated by ADE.
// Cadence Design Systems, Inc.

// This is an autoGenerated file, any changes done to this file may get lost.

`include "disciplines.vams"
`include "userDisciplines.vams"

module cds_globals;

// Global Signals
   electrical \gnd! ;
   ground \gnd! ;

// Design Variables
   dynamicparam real temperature = 27;
   dynamicparam real test_val_gui = 10;
   dynamicparam real clk_f = 1G;

endmodule

Fullscreen testcase_ams_log.txt Download

xrun(64): 25.03-s005: (c) Copyright 1995-2025 Cadence Design Systems, Inc.
TOOL:	xrun(64)	25.03-s005: Started on Oct 06, 2025 at 10:48:41 PDT
xrun
	-f xrunArgs
		-UNBUFFERED
		-cdslib ./cds.lib
		-errormax 50
		-status
		-nowarn DLNOHV
		-nowarn DLCLAP
		-v93
		-incdir /Project_Path/ProjectX/cadence/
		-ade
		-timescale 1ns/1ns
		-vtimescale 1ns/1ns
		-delay_mode None
		-novitalaccl
		-access r
		-noparamerr
		-amspartinfo ../psf/partition.info
		-rnm_partinfo
		-modelincdir /Project_Path/ProjectX/cadence/
		./spiceModels.scs
		./amsControlSpectre.scs
		-input ./probe.tcl
		-run
		-exit
		-xmsimargs "+amsrawdir ../psf"
		-spectre_args "-ahdllibdir /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.2/sharedData/CDS/ahdl/input.ahdlSimDB"
		-spectre_args +logstatus
		-simcompatible_ams spectre
		-name testcases.tb_testcase_ams_include_vars:config
		-allowredefinition
		-amsbind
		-top testcases.tb_testcase_ams_include_vars:schematic
		-top cds_globals
		./netlist.vams
		./ie_card.scs
		-f ./textInputs
			-amscompilefile "file:/Project_Path/ProjectX/cadence/testcases/testcase_veriloga/veriloga/veriloga.va ftype:va lib:testcases cell:testcase_veriloga view:veriloga"
		./cds_globals.vams
		-l ../psf/xrun.log
		-spectre_args "+preset=mx +mt"
file: ./netlist.vams
	module testcases.tb_testcase_ams_include_vars:schematic
		errors: 0, warnings: 0
file: ./cds_globals.vams
	module worklib.cds_globals:vams
		errors: 0, warnings: 0
xmvlog: *W,SPDUSD: Include directory /Project_Path/ProjectX/cadence/ given but not used.
	Total errors/warnings found outside modules and primitives:
		errors: 0, warnings: 1
xmvlog: Memory Usage - Current physical: 25.8M, Current virtual: 53.5M, Peak physical: 25.8M
xmvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 100.0% cpu)
		Caching library 'testcases' ....... Done
		Caching library 'worklib' ....... Done
	Elaborating the design hierarchy:
xmelab: *N,MSFLON: Xcelium will initiate mixed signal elaboration, Reason: .amsbind.scs.
	Top level design units:
		tb_testcase_ams_include_vars
		cds_globals
testcase_veriloga #(.test_var_file(cds_globals.test_val_file), .test_var_gui(cds_globals.test_val_gui)) I0 (.out_file( out_file ), .out_gui( out_gui ), .clk( clk ));
                                                           |
xmelab: *E,CUVHNF (./netlist.vams,28|59): Hierarchical name component lookup failed at 'cds_globals.test_val_file'.
xmelab: Memory Usage - Final: 63.0M, Peak: 63.0M, Peak virtual: 145.8M
xmelab: CPU Usage - 0.1s system + 0.0s user = 0.1s total (0.1s, 100.0% cpu)
xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 1), exiting.
TOOL:	xrun(64)	25.03-s005: Exiting on Oct 06, 2025 at 10:48:54 PDT  (total: 00:00:13)

AA202510057331 2 days ago in reply to Saloni Chhabra

Hi Saloni,

Thanks for your reply.

The verilog module testcase_veriloga is shown below

Fullscreen 7268.veriloga.txt Download

`include "constants.vams"
`include "disciplines.vams"

module testcase_veriloga(clk, out_gui, out_file);

input clk;
output out_gui, out_file;
electrical clk, out_gui, out_file;

parameter real test_var_gui = 0;
parameter real test_var_file = 0;

analog begin

@(initial_step) begin
$display("Testcase VerilogA %M: variable test_var_gui value passed is %f", test_var_gui);
$display("Testcase VerilogA %M: variable test_var_file value passed is %f", test_var_file);
end
V(out_gui) <+ transition(test_var_gui, 0, 1p, 1p);
V(out_file) <+ transition(test_var_file, 0, 1p, 1p);
end


endmodule

The testbench itself contains an instance of this module and a clock source just to make sure the engine is running. It runs a transient sim.

A. Spectre only scenario with my_vars.scs included in model libraries.

Include the file "my_vars.scs" (below) in the model_libraries section.
Set the spectre redefinedparams option to warning or ignore to avoid errors from variable "test_val_file" double definition (The one in the file and the unintended auto-imported one in the GUI)
Running the simulation and ignoring the unset variable warning (ASSEMBLER-1610), as we already know the definition in the file sets that variable
This case runs normally, and the variables are correctly passed to the VerilogA module as indicated by its output voltages and messages.

Fullscreen 5611.testcase_spectreonly_netlist.txt Download

// Point Netlist Generated on: Oct  6 10:21:05 2025
// Generated for: spectre
// Design Netlist Generated on: Oct  6 10:21:05 2025
// Design library name: testcases
// Design cell name: tb_testcase_ams_include_vars
// Design view name: config
simulator lang=spectre
include "ade_e.scs"
global 0
parameters test_val_file temperature=27 test_val_gui=10 clk_f=1G
include "/Project_Path/ProjectX/cadence/my_vars.scs"

// Library name: testcases
// Cell name: tb_testcase_ams_include_vars
// View name: schematic
// Inherited view list: spectre spice pspice verilog verilogams
// behavioral functional systemVerilog schematic veriloga vhdl vhdlams
// wreal
V0 (clk 0) vsource dc=1 type=pulse val0=0 val1=1 period=1/clk_f \
        delay=-(1p)/2 rise=1p fall=(1p) width=0.5*(1/clk_f-(1p)-((1p)))
I0 (clk out_gui out_file) testcase_veriloga test_var_gui=test_val_gui \
        test_var_file=test_val_file
simulatorOptions options psfversion="1.4.0" temp=27 tnom=27 scalem=1.0 \
    scale=1.0 gmin=1e-12 rforce=1 redefinedparams=warning maxnotes=5 \
    maxwarns=5 digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=sqldb 
tran tran stop=3n write="spectre.ic" writefinal="spectre.fc" \
    annotate=status 
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub
ahdl_include "/Project_Path/ProjectX/cadence/testcases/testcase_veriloga/veriloga/veriloga.va"

Fullscreen 5611.testcase_spectreonly_log.txt Download

Spectre (R) Circuit Simulator
Version 24.1.0.288.isr5 64bit -- 3 Apr 2025
Copyright (C) 1989-2025 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: username   Host: hostname   HostID: D90AF471   PID: 4075422
Memory  available: 474.9463 GB  physical: 540.1019 GB
Linux   : Rocky Linux release 9.6 (Blue Onyx)
CPU Type: Intel(R) Xeon(R) Gold 5115 CPU @ 2.40GHz
        Socket: Processors [Frequency] (Hyperthreaded Processor)
        0:       0 [2799.8] ( 20 ),  2 [2800.2] ( 22 ),  4 [3200.0] ( 24 )
                 6 [3200.0] ( 26 ),  8 [2800.0] ( 28 ), 10 [2800.1] ( 30 )
                12 [3200.0] ( 32 ), 14 [2798.9] ( 34 ), 16 [2744.7] ( 36 )
                18 [3200.0] ( 38 )
        1:       1 [2800.0] ( 21 ),  3 [2800.1] ( 23 ),  5 [2800.0] ( 25 )
                 7 [2450.5] ( 27 ),  9 [2758.3] ( 29 ), 11 [2800.1] ( 31 )
                13 [2800.0] ( 33 ), 15 [2800.0] ( 35 ), 17 [2800.0] ( 37 )
                19 [2780.0] ( 39 )
        
System load averages (1min, 5min, 15min) : 221.9 %, 221.8 %, 223.4 %
Hyperthreading is enabled
HPC is enabled


Simulating `input.scs' on hostname at 10:21:07 AM, Mon Oct 6, 2025 (process id: 4075422).
Current working directory: /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/1/DLL_SAR_NEW_tb_testcase_ams_include_vars_1/netlist
Command line:
    /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/bin/spectre  \
        -64 input.scs +escchars +log ../psf/spectre.out -format psfxl  \
        -raw ../psf +preset=mx +mt +lqtimeout 900 -maxw 5 -maxn 5 -env  \
        ade  \
        +adespetkn=0001089D13A302B663E41FB550AF0DF415A679A322D5069144BF588C12F604E07EF416DC01A319B562BB63D30AA94CE045A374D82AFD2CB778D05DFA1ADC4F9259DE79D15D9175FF349871C618F215BB58EA77C714A91AE358F726822CD674D30EAE79D118F874D3349879D118F874D334981132E27A8E515C7B000036AA  \
        -ahdllibdir  \
        /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB  \
        +logstatus

Simulation Id: 83jaAALHXd9eImmF
Licensing Information:
[10:21:07.219994] Configured Lic search path (24.01-s002): 5280@linlic8.engr.oregonstate.edu:7188@linlic8.engr.oregonstate.edu

Licensing Information:
[10:21:08.089672] Periodic Lic check successful

Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libphilips_I_sh.so ...
Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file:  /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/1/DLL_SAR_NEW_tb_testcase_ams_include_vars_1/netlist/input.scs

Notice from spectre during circuit read-in.
    Pre_Configuration file used: /usr/local/apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/preset.precfg
    Configuration file used: `/usr/local/apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/preset.cfg'.

Reading link:  /usr/local/apps/cadence
Reading link:  /usr/local/apps
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/preset.precfg
Reading file:  /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/1/DLL_SAR_NEW_tb_testcase_ams_include_vars_1/netlist/ade_e.scs
Reading file:  /Project_Path/ProjectX/cadence/my_vars.scs
Reading file:  /Project_Path/ProjectX/cadence/testcases/testcase_veriloga/veriloga/veriloga.va
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading file:  /nfs/guille/a2/rh80apps/cadence/spectre/spectre241/tools.lnx86/spectre/etc/configs/preset.cfg
Time for NDB Parsing: CPU = 281.367 ms, elapsed = 798.539 ms.
Time accumulated: CPU = 481.917 ms, elapsed = 798.541 ms.
Peak resident memory used = 196 Mbytes.


Warning from spectre during circuit read-in.
    WARNING (SFE-2297): "/Project_Path/ProjectX/cadence/my_vars.scs" 4: Parameter `test_val_file' is already defined in the same block, previous definition is ignored.

Created directory /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB/ (775)
Created directory /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB//603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/ (775)
Reading file:  /scratch/simulation/ProjectX/DLL_SAR_NEW/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.46/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB/603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_testcase_veriloga.so
Created directory /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB//603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/obj/optimize/5.0 
Copying files from directory /scratch/simulation/ProjectX/DLL_SAR_NEW/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.46/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB/603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/ to directory /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB//603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/
Finished copying files from /scratch/simulation/ProjectX/DLL_SAR_NEW/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.46/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB/603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/ to /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.0/sharedData/CDS/ahdl/input.ahdlSimDB/input.ahdlSimDB//603bb87dffd120771d48eb249ec3b531.testcase_veriloga.ahdlcmi/Linux-64/.
The simulator has reused the existing Verilog-A libraries for this simulation run. If you do not want to use these libraries, set the 'CDS_AHDL_REUSE_LIB' environment variable to 'NO' and rerun the simulation.
Existing shared object for module testcase_veriloga is up to date.
Installed compiled interface for testcase_veriloga.
Time for Elaboration: CPU = 27.87 ms, elapsed = 184.978 ms.
Time accumulated: CPU = 509.898 ms, elapsed = 983.634 ms.
Peak resident memory used = 205 Mbytes.

 Start ADE Session ID: 83jaAALHXd9eImmF

Time for EDB Visiting: CPU = 4.492 ms, elapsed = 8.65388 ms.
Time accumulated: CPU = 514.567 ms, elapsed = 992.465 ms.
Peak resident memory used = 206 Mbytes.


Notice from spectre during initial setup.
    Ignorevaref=yes is ignored since all nodes are connected to Verilog-A modules.
Notice from spectre during topology check.
    Only one connection to the following 3 nodes:
        0
        out_gui
        out_file
Notice from spectre during initial setup.
    Multithreading is disabled due to the size of the design being too small.


Netlist title:
        // Point Netlist Generated on: Oct  6 10:21:05 2025


Global user options:
         psfversion = 1.4.0
               temp = 27
               gmin = 1e-12
             rforce = 1
           maxnotes = 5
           maxwarns = 5
             digits = 5
               cols = 80
             pivrel = 0.001
           sensfile = ../psf/sens.output
     checklimitdest = sqldb
               save = allpub
               tnom = 27
             scalem = 1
              scale = 1

Scoped user options:

Circuit inventory:
              nodes 3
  testcase_veriloga 1     
            vsource 1     

Analysis and control statement inventory:
               info 7     
               tran 1     

Output statements:
             .probe 0     
           .measure 0     
               save 0     

Design checks inventory:
          paramtest 1     


Notice from spectre during initial setup.
    Protected devices exist and are not included in the circuit inventory.
    Spectre X preset=mx enabled.

Time for parsing: CPU = 5.661 ms, elapsed = 8.35586 ms.
Time accumulated: CPU = 520.384 ms, elapsed = 1.00098 s.
Peak resident memory used = 210 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
   -   (Spectre X) Multi-threading. The recommended number of threads is 1, consider adding +mt=1 on command line.
~~~~~~~~~~~~~~~~~~~~~~

***********************************************
Transient Analysis `tran': time = (0 s -> 3 ns)
***********************************************
Testcase VerilogA I0: variable test_var_gui value passed is 10.000000
Testcase VerilogA I0: variable test_var_file value passed is 13.256000
Convergence achieved in 2 iterations.
DC simulation time: CPU = 833 us, elapsed = 838.041 us.

Opening the PSFXL file ../psf/tran.tran.tran ...
Important parameter values:
    start = 0 s
    outputstart = 0 s
    stop = 3 ns
    step = 3 ps
    maxstep = 60 ps
    ic = all
    useprevic = no
    skipdc = no
    reltol = 1e-03
    abstol(V) = 1 uV
    abstol(I) = 1 pA
    temp = 27 C
    tnom = 27 C
    tempeffects = all
    errpreset = moderate
    method = trap
    lteratio = 3.5
    relref = allglobal
    cmin = 0 F
    gmin = 1 pS
    rabsshort = 1 mOhm


Notice from spectre during transient analysis `tran'.
    Multithreading is disabled due to the size of the design being too small.


Output and IC/nodeset summary:
                 save   1       (current)
                 save   3       (voltage)

    tran: time = 123.5 ps    (4.12 %), step = 60 ps           (2 %)
    tran: time = 243.5 ps    (8.12 %), step = 60 ps           (2 %)
    tran: time = 423.5 ps    (14.1 %), step = 60 ps           (2 %)
    tran: time = 540.5 ps      (18 %), step = 38 ps        (1.27 %)
    tran: time = 720.5 ps      (24 %), step = 60 ps           (2 %)
    tran: time = 840.5 ps      (28 %), step = 60 ps           (2 %)
    tran: time = 999.5 ps    (33.3 %), step = 49.5 ps      (1.65 %)
    tran: time = 1.172 ns    (39.1 %), step = 60 ps           (2 %)
    tran: time = 1.292 ns    (43.1 %), step = 60 ps           (2 %)
    tran: time = 1.456 ns    (48.5 %), step = 43.75 ps     (1.46 %)
    tran: time = 1.606 ns    (53.5 %), step = 60 ps           (2 %)
    tran: time = 1.726 ns    (57.5 %), step = 60 ps           (2 %)
    tran: time = 1.906 ns    (63.5 %), step = 60 ps           (2 %)
    tran: time = 2.049 ns    (68.3 %), step = 46.62 ps     (1.55 %)
    tran: time = 2.229 ns    (74.3 %), step = 60 ps           (2 %)
    tran: time = 2.349 ns    (78.3 %), step = 60 ps           (2 %)
    tran: time = 2.499 ns    (83.3 %), step = 45.19 ps     (1.51 %)
    tran: time = 2.668 ns    (88.9 %), step = 60 ps           (2 %)
    tran: time = 2.788 ns    (92.9 %), step = 60 ps           (2 %)
    tran: time = 2.954 ns    (98.5 %), step = 45.91 ps     (1.53 %)
Number of accepted tran steps =             71

Maximum value achieved for any signal of each quantity: 
V: V(out_file) = 13.26 V
I: I(V0:p) = 0 A

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Post-Transient Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


During simulation, the CPU load for active processors is :
         0 (7.4 %)       1 (22.3 %)      2 (2.2 %)       3 (11.6 %)
         4 (2.2 %)       5 (4.3 %)       6 (2.1 %)       7 (8.4 %)
         8 (7.4 %)       9 (5.3 %)      10 (2.1 %)      11 (9.9 %)
        12 (8.7 %)      13 (6.3 %)      14 (4.2 %)      15 (3.2 %)
        16 (43.6 %)     17 (26.3 %)     18 (4.3 %)      19 (2.1 %)
        20 (6.5 %)      21 (3.2 %)      22 (2.2 %)      23 (26.6 %)
        24 (5.4 %)      25 (9.6 %)      26 (36.8 %)     27 (6.3 %)
        28 (75.0 %)     29 (21.1 %)     30 (2.1 %)      31 (20.7 %)
        32 (4.2 %)      33 (25.5 %)     34 (1.1 %)      35 (11.8 %)
        36 (2.2 %)      37 (2.1 %)      38 (34.8 %)     39 (3.2 %)
        Total: 484.3%
Initial condition solution time: CPU = 904 us, elapsed = 910.044 us.
Intrinsic tran analysis time:    CPU = 8.246 ms, elapsed = 8.6081 ms.
Total time required for tran analysis `tran': CPU = 12.168 ms, elapsed = 12.538 ms, util. = 97%.
Time accumulated: CPU = 559.597 ms, elapsed = 1.04084 s.
Peak resident memory used = 214 Mbytes.

finalTimeOP: writing operating point information to rawfile.

Opening the PSF file ../psf/finalTimeOP.info ...
modelParameter: writing model parameter values to rawfile.

Opening the PSF file ../psf/modelParameter.info ...
element: writing instance parameter values to rawfile.

Opening the PSF file ../psf/element.info ...
outputParameter: writing output parameter values to rawfile.

Opening the PSF file ../psf/outputParameter.info ...
designParamVals: writing netlist parameters to rawfile.

Opening the PSFASCII file ../psf/designParamVals.info ...
primitives: writing primitives to rawfile.

Opening the PSFASCII file ../psf/primitives.info.primitives ...
subckts: writing subcircuits to rawfile.

Opening the PSFASCII file ../psf/subckts.info.subckts ...
Licensing Information:
Lic Summary:
[10:21:08.292339] Cdslmd servers:5280@linlic8.engr.oregonstate.edu:7188@linlic8.engr.oregonstate.edu
[10:21:08.816683] Feature usage summary:
[10:21:08.816688] Virtuoso_Multi_mode_Simulation
[10:21:08.816689] Spectre_X_MMSIM_Lk


Aggregate audit (10:21:08 AM, Mon Oct 6, 2025):
Time used: CPU = 568 ms, elapsed = 1.05 s, util. = 54%.
Time spent in licensing: elapsed = 161 ms, percentage of total = 15.3%.
Peak memory used = 215 Mbytes.
Simulation started at: 10:21:07 AM, Mon Oct 6, 2025, ended at: 10:21:08 AM, Mon Oct 6, 2025, with elapsed time (wall clock): 1.05 s.
spectre completes with 0 errors, 1 warning, and 10 notices.

B. AMS scenario with my_vars.scs included in model libraries.

Include the file "my_vars.scs" (below) in the model_libraries section.
Set the spectre redefinedparams option to warning or ignore to avoid errors from variable "test_val_file" double definition (The one in the file and the unintended auto-imported one in the GUI)
Running the simulation and ignoring the unset variable warning (ASSEMBLER-1610), as we already know the definition in the file sets that variable
Deleting the empty "test_val_file" unset variable created before from the test "Design Variables" section. Not sure if this is necessary.
This case gives a sim error and upon checking it shows
xmelab: *E,CUVHNF (./netlist.vams,28|59): Hierarchical name component lookup failed at 'cds_globals.test_val_file'.

The log and netlist are seen below as testcase_ams_log and testcase_ams_netlist. The auto-generated cds_globals file is also shown as testcase_ams_cds_globals

Fullscreen 5611.testcase_ams_netlist.txt Download

// AMS netlist generated by the AMS Unified netlister // IC subversion: IC25.1-64b.38 // Xcelium version: 25.03-s005 // Copyright(C) 2005-2009, Cadence Design Systems, Inc // User: username Pid: 3050583 // Design library name: testcases // Design cell name: tb_testcase_ams_include_vars // Design view name: config // Solver: Spectre `include "disciplines.vams" `include "userDisciplines.vams" // HDL file - testcases, testcase_veriloga, veriloga. // Library - testcases, Cell - tb_testcase_ams_include_vars, View - schematic // LAST TIME SAVED: Oct 6 10:19:47 2025 // NETLIST TIME: Oct 6 10:39:59 2025 `worklib testcases `view schematic `timescale 1ns / 1ns (* cds_ams_schematic *) module tb_testcase_ams_include_vars ( ); wire clk; wire out_gui; wire out_file; testcase_veriloga #(.test_var_file(cds_globals.test_val_file), .test_var_gui(cds_globals.test_val_gui)) I0 (.out_file( out_file ), .out_gui( out_gui ), .clk( clk )); vsource #(.dc(1), .type("pulse"), .val0(0), .val1(1), .period(1/cds_globals.clk_f), .delay(-(1e-12)/2), .rise(1e-12), .fall(1e-12), .width(0.5*(1/cds_globals.clk_f-(1e-12)-((1e-12))))) V0 (clk, cds_globals.\gnd! ); endmodule `noworklib `noview

Fullscreen 5611.testcase_ams_cds_globals.txt Download

// Verilog-AMS cds_globals module for top-level cell: // testcases/tb_testcase_ams_include_vars. // Generated by ADE. // Cadence Design Systems, Inc. // This is an autoGenerated file, any changes done to this file may get lost. `include "disciplines.vams" `include "userDisciplines.vams" module cds_globals; // Global Signals electrical \gnd! ; ground \gnd! ; // Design Variables dynamicparam real temperature = 27; dynamicparam real test_val_gui = 10; dynamicparam real clk_f = 1G; endmodule

Fullscreen 5611.testcase_ams_log.txt Download

xrun(64): 25.03-s005: (c) Copyright 1995-2025 Cadence Design Systems, Inc. TOOL: xrun(64) 25.03-s005: Started on Oct 06, 2025 at 10:48:41 PDT xrun -f xrunArgs -UNBUFFERED -cdslib ./cds.lib -errormax 50 -status -nowarn DLNOHV -nowarn DLCLAP -v93 -incdir /Project_Path/ProjectX/cadence/ -ade -timescale 1ns/1ns -vtimescale 1ns/1ns -delay_mode None -novitalaccl -access r -noparamerr -amspartinfo ../psf/partition.info -rnm_partinfo -modelincdir /Project_Path/ProjectX/cadence/ ./spiceModels.scs ./amsControlSpectre.scs -input ./probe.tcl -run -exit -xmsimargs "+amsrawdir ../psf" -spectre_args "-ahdllibdir /scratch/simulation/ProjectX/testcases/tb_testcase_ams_include_vars/maestro/results/maestro/Interactive.2/sharedData/CDS/ahdl/input.ahdlSimDB" -spectre_args +logstatus -simcompatible_ams spectre -name testcases.tb_testcase_ams_include_vars:config -allowredefinition -amsbind -top testcases.tb_testcase_ams_include_vars:schematic -top cds_globals ./netlist.vams ./ie_card.scs -f ./textInputs -amscompilefile "file:/Project_Path/ProjectX/cadence/testcases/testcase_veriloga/veriloga/veriloga.va ftype:va lib:testcases cell:testcase_veriloga view:veriloga" ./cds_globals.vams -l ../psf/xrun.log -spectre_args "+preset=mx +mt" file: ./netlist.vams module testcases.tb_testcase_ams_include_vars:schematic errors: 0, warnings: 0 file: ./cds_globals.vams module worklib.cds_globals:vams errors: 0, warnings: 0 xmvlog: *W,SPDUSD: Include directory /Project_Path/ProjectX/cadence/ given but not used. Total errors/warnings found outside modules and primitives: errors: 0, warnings: 1 xmvlog: Memory Usage - Current physical: 25.8M, Current virtual: 53.5M, Peak physical: 25.8M xmvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 100.0% cpu) Caching library 'testcases' ....... Done Caching library 'worklib' ....... Done Elaborating the design hierarchy: xmelab: *N,MSFLON: Xcelium will initiate mixed signal elaboration, Reason: .amsbind.scs. Top level design units: tb_testcase_ams_include_vars cds_globals testcase_veriloga #(.test_var_file(cds_globals.test_val_file), .test_var_gui(cds_globals.test_val_gui)) I0 (.out_file( out_file ), .out_gui( out_gui ), .clk( clk )); | xmelab: *E,CUVHNF (./netlist.vams,28|59): Hierarchical name component lookup failed at 'cds_globals.test_val_file'. xmelab: Memory Usage - Final: 63.0M, Peak: 63.0M, Peak virtual: 145.8M xmelab: CPU Usage - 0.1s system + 0.0s user = 0.1s total (0.1s, 100.0% cpu) xrun: *E,ELBERR: Error (*E) or soft error (*SE) occurred during elaboration (status 1), exiting. TOOL: xrun(64) 25.03-s005: Exiting on Oct 06, 2025 at 10:48:54 PDT (total: 00:00:13)

Saloni Chhabra 1 day ago in reply to AA202510057331

Instead of deleting the variable 'test_var_file' from ADE, you need to assign any dummy value to it e.g. 0. This value will be overwritten by my_vars.scs. Here's how my Maestro view and outputs look for your example. test_var_file is set to 2 through .scs file.

Messages in xrun.log:

Testcase VerilogA testcase_veriloga_sim.I0: variable test_var_gui value passed is 1.000000
Testcase VerilogA testcase_veriloga_sim.I0: variable test_var_file value passed is 2.000000
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