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  1. Community Forums
  2. PCB Design

PCB Design

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

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PCB Design

Latest Posts

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  • Discussion

    ORCIS-6085 error.

    Category: PCB Design

    By youndersun

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    •

    started over 5 years ago

    0 replies • 12759 views
  • Discussion

    Could this function "Online DRC" be set as default disable in Capture?

    Category: PCB Design

    By RaymondG

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    •

    started over 5 years ago

    0 replies • 1855 views
  • Discussion

    Internal unused via pad suppression not working

    Category: PCB Design

    By atoddrich

    $usertype

    •

    updated over 5 years ago by atoddrich

    2 replies • 14784 views
  • Discussion

    Propagation Delay Delta tolerance value in mils

    Category: PCB Design

    By GK MN

    $usertype

    •

    updated over 5 years ago by GK MN

    2 replies • 14857 views
  • Discussion

    pcb footprint creation

    Category: PCB Design

    By Dinesh Moka

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    •

    started over 5 years ago

    0 replies • 12227 views
  • Discussion

    Scalpel skill file

    Category: PCB Design

    By atoddrich

    $usertype

    •

    updated over 5 years ago by redwire

    3 replies • 13372 views
  • Discussion

    Show preview of footprint and schematic symbol in external database management app

    Category: PCB Design

    By MrMarcus

    $usertype

    •

    updated over 5 years ago by RFinley

    1 replies • 12599 views
  • Discussion

    OrCAD tcl script for Export Hierarchy?

    Category: PCB Design

    By ron2015schmitt

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    •

    updated over 5 years ago by jpolakow

    2 replies • 14315 views
  • Discussion

    PCB Editor Tool for Matched Lengths in DDR Fly-By Topology?

    Category: PCB Design

    By Gipper

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    •

    updated over 5 years ago by Gipper

    8 replies • 19185 views
  • Discussion

    When the net schedule is set in the PCB editor and auto-routing is executed, the routing is different from the set schedule.

    Category: PCB Design

    By wjavos

    $usertype

    •

    updated over 5 years ago by steve

    3 replies • 13097 views
  • Discussion

    WARNING(ORNET-1119): The part/device cannot be simulated. No PSpiceTemplate found on J1, ignoring this part/device from simulation netlist

    Category: PCB Design

    By desertbird

    $usertype

    •

    updated over 5 years ago by desertbird

    1 replies • 7958 views
  • Discussion

    How to solve the via shorting issue?

    Category: PCB Design

    By Vish7

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    •

    updated over 5 years ago by Lock2002

    3 replies • 13716 views
  • Discussion

    Cant create netlist in capture cis

    Category: PCB Design

    By desertbird

    $usertype

    •

    updated over 5 years ago by Alok Tripathi

    3 replies • 13060 views
  • Discussion

    can't route differential net

    Category: PCB Design

    By pupradar

    $usertype

    •

    updated over 5 years ago by AvengerThanos

    3 replies • 2484 views
  • Discussion

    difference between the 4 layer & 6 layer

    Category: PCB Design

    By Sutha

    $usertype

    •

    updated over 5 years ago by AvengerThanos

    1 replies • 2347 views
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