• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. RF Design
  3. How to avoid Hidden State in VerilogA model for Spectre...

Stats

  • Locked Locked
  • Replies 12
  • Subscribers 66
  • Views 25185
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to avoid Hidden State in VerilogA model for SpectreRF

RFStuff
RFStuff over 12 years ago

 Dear All,

I am a beginner in verilogA .

I wrote a code but when I ran PSS it showed hidden state in the code and didn't run.

My behavioural model is as below:-

 

 

// VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga

`include "constants.vams"
`include "disciplines.vams"

module HARD_LIMIT_GM(in,out);
  inout in,out;
  parameter real vtrans = 0;
  parameter real tdelay = 0 from [0:inf);
  parameter real trise = 1p from (0:inf);
  parameter real tfall = 1p from (0:inf);
  parameter real Gm=-5m;
  electrical in,out;
  real vout_val;
  analog begin
 
         @ (cross(V(in) - vtrans, 1))  vout_val = 1;
         @ (cross(V(in) - vtrans, -1)) vout_val = 0;
 
         I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall); 
  end   
endmodule

 

Could anybody please tell how I can avoid the hidden state  (vout_val ) ?

 

Kind Regards,

  • Cancel
  • seadoftj
    seadoftj over 8 years ago

    Hi Andrew,

     I will like to know while this Normalised LMS algorithm could not be supported in PSS analysis due to the hidden state variable "WtsReg".

    Can you please help proffer solution or suggestion to the code in verilogA.

    // VerilogA for IM2_Cancellation, LMS, veriloga

    `include "constants.vams"
    `include "disciplines.vams"

    module LMS(clk,Inp_Sig,Error, Wts);

    input clk, Error,Inp_Sig;
    electrical clk, Error,Inp_Sig;
    output Wts;
    electrical Wts;

    parameter real mu=0.2 ; //varies between 0 to 2

    integer  vth;
    integer Clk;
    real ErrorReg;
    real WtsReg;
    integer Vin;
    real Quot;

    analog begin
            Clk = (V(clk)> 0.5)? 1:0;

            @(initial_step)
            begin

                    WtsReg = 0;
                    V(Wts) <+ 0;
            end

            if (V(Inp_Sig)) begin

                    ErrorReg =  V(Error);
                    V(Wts) <+ WtsReg;

            end

            @ (cross(Clk - 0.5, +1)) // rising edge of clock signal
            begin
                    ErrorReg =  V(Error);
                    Quot = V(Inp_Sig)/(V(Inp_Sig)*V(Inp_Sig));

                    WtsReg = WtsReg + mu * ErrorReg * Quot;

            end
    end
    endmodule

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Andrew Beckett
    Andrew Beckett over 8 years ago

    Did you read the http://www.designers-guide.org/Analysis/hidden-state.pdf paper I pointed at earlier in this thread? The problem is that you are relying on sampling the signal at the clock edge into the variable WtsReg which is then a hidden state variable. You need to employ one of the strategies discussed in that paper so that this state is represented as an electrical node rather than a variable; variables have to be updated on every iteration.

    It's also not a good idea to have the contribution statement (the V(Wts)<+WtsReg;) inside a conditional statement - in fact I'm not sure that's really doing anything useful (so remove the surrounding if() statement).

    This thread seems to have become a bit of a dumping ground for questions on hidden state; the forum guidelines ask forum users not to post on the end of old threads to avoid muddying the answers and making it harder for people to find specific answers to specific questions.

    Kind Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
<

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information