pnoise spurs at multiples of clock frequency.

 Yes I did try this and something similar by changing both start and end points to not be on exact multiple.

 These help upto some extent,  probably ok for now and thanks for the support.

 Thanks,

-Vamshi

 Although changing the start and stop and keeping dec wouldn't help, because it will still start each decade on an exact exponent of 10. But at least log should help make it far more likely that you miss the exact multiples, whilst keeping the same type of distribution that dec would have.

Andrew.

Hi Andrew,

I am having problems with a spur as you said before in this post. I am calculating the jitter from the pnoise simulation.

The situation is as follows:

I am developing a distribution path for a 100MHz clock. When the phase noise is simulated, the results show a huge spur at the frequency of 100MHz. The integration of the noise power density spectrum neglecting the spur provides a jitter smaller than 1ps while the spur provides a jitter over 1ns. The top value of the spur compared with the noise at 1Hz stay constant independently of the cell simulated: buffers, inverters…
Simulation parameters:

· Toot: cadence spectre APS
· Beat Freq:100MHz
· Num Harmonics: 60
· Points per Dec: 80
· Sweeptype:absolute
· Noise type: jitter/Sources

as mentioned in earlier answers, less point/dec filter the peak more or less while the other noise spectrum stay +- the same.

There is some explanation for the spur?

Best regards

Manuel

Dear Manuel,

I am not Andrew and certainly do not possess his expertise, but if I understand your issue correctly, I think I can provide some insight.

If you are stimulating your clock distribution path with a 100 MHz clock, and you examine its phase noise spectrum with a fundamental frequency of 100 MHz, you will definitely observe "spurs" (as you call them) at 100 MHz. The spurs are associated with the sampling process - effectively a phase sample is created every period of your 100 MHz clock. Hence, the resulting spectrum will be periodic and limited to fs/2 in its frequency content. Hence, I would recommend you perform your integration up to 50 MHz. Does this make sense to you?

I'm also a little confused as to the goal of your simulation. Are you trying to measure the random noise due to the distribution path - or are you trying to assess the deterministic jitter of your clock distribution path? There may be an alternative to your strategy that I could suggest if you are interested and provide a bit more detail on the goal of your effort.

Shawn

Dear Manuel,

Thank you for your added application information. It is helpful!

> My case is a clock of 100MHz for an ADC and the specification was: Jitter < X fsRMS.

> I am interested in all contribution to the jitter so I took a large bandwidth in spite of the low frequencies has no impact..

If you are using a 100 MHz A/D, the signal frequencies of interest must be well under 50 MHz. However, it is possible that the bandwidth of the ADC clock input may exceed the bandwidth of the input signal. If you happen to know the bandwidth of the ADC clock input, I might propose using that bandwidth as the maximum frequency to use in your clock jitter computation.

If you have simulated the random phase noise component of a your clock signal, you can estimate its random jitter component by integrating the phase noise between the minimum and maximum frequencies of interest to compare to your requirement.

> The effects of the power supply i have to simulate them with the PXF right?

As far as deterministic jitter components are concerned, for the clock path you are simulating, you might impose the amount of supply noise you expect on the buffer supplies and examine the resulting peak-to-peak time interval error (TIE) at the ADC input port. This will provide an estimate of the deterministic jitter. There is some frequency dependence to the peak-to-peak output TIE - so the frequency content of your supply noise is important to include in the simulation. This simulation can be a simple transient simulation. 

I hope this provides some help...

Shawn

Use pnoise jitter analysis with the fullspectrum option and make sure that the maxacfreq parameter of the pss analysis has a sufficiently large value (see http://www.designers-guide.org/Forum/YaBB.pl?num=1438976388 for some more details). Integrate the noise power from 0 Hz to half of the pss fundamental frequency. You can find some more information (also about pxf) in the thread starting at http://www.designers-guide.org/Forum/YaBB.pl?num=1224609785 and the links given there.

Jc(k) is the k-cycle jitter, that is the standard deviation of the duration of k cycles of the signal.