How to use MOSFET as a switch to introduce a capacitor into a LC tank in VCO?

Alex,

Transient can save the final operating point (at the end of the simulation) and that's what it may be displaying (it depends if you turn that on for the transient analysis). You can see in the results browser if there is a final transient operating point. It doesn't record the time for the operating point in that case - but normally it would just be at the very end of the transient (the name in the netlist is pretty clear too...). I thought the form for the annotate transient operating point said "final" in it somewhere but I'd have to check as my memory may be failing me at 9pm on a Friday night ;-)

By the way, the extra images didn't bother me - it was just that posting the images as part of your post means that they show up inline which is a bit easier for users (I meant to include a smiley in my comment about extra pictures!)

Regards,

Andrew.

Andrew,

Thanks for the clarification. 

I thought you have extra opinion on Asian people and that's why you think the lady with an airplane in the Ads picture has Asian appearance.

That indeed made me think you are sensitive about that. But turned out not. A smile is always important.

By the way, the lady you saw was not from Asian from my experience :-)

Have a very good weekend!

Regards,

Alex

Dear Alex,

> Is there any wrong for the ideal case's output and/ or the design?

I took a look at your basic VCO circuit. I do not know if your inductors are ideal or have a finite Q. It also appears as if there are no parasitic layout capacitances nor resistances. Each of these will lower your negative resistance in magnitude as well as reduce oscillator steady-state amplitude. They will also impact the oscillation frequency. If these are not included, your waveform amplitude may be unrealistically large - which could be why you are observing the large voltage swing.

As for your switches, I might suggest a different MOS switch and capacitor topology to assist in the control of your MOS switches. Since your VCO is basically a differential circuit, you can take advantage of that fact by splitting each added capacitor Cb0, Cb1, Cb2, and Cb3 into sets of 2 series capacitors. For example, replace Cb0 with two capacitors Cb0a and Cb0b where Cb0a = Cb0b = 2*Cb0. One node of Cb0a connects to node +V/2, and one node of Cb0b connects to node -V/2. Place the MOS switch for Cb0a and Cb0b between the two capacitors. In this fashion, the drain and source of the MOS device is at an AC virtual ground since the oscillator is differential. The range of DC values of the MOS drain and source will be less than in your present topology. As a result, setting the gate voltage to assure the switch is on or off may be easier. In the topology you have shown, one side of each switch sees the full swing of one side of the differential VCO output. As a result, it will be more difficult to provide robust MOS switch control.

I hope this makes sense Alex.

Shawn

Hello Shawn,

smlogan said:

I took a look at your basic VCO circuit. I do not know if your inductors are ideal or have a finite Q. It also appears as if there are no parasitic layout capacitances nor resistances. Each of these will lower your negative resistance in magnitude as well as reduce oscillator steady-state amplitude. They will also impact the oscillation frequency. If these are not included, your waveform amplitude may be unrealistically large - which could be why you are observing the large voltage swing.

The device model of the inductors are adopted from normal ones in which I did not set Res (0 by default), so I would think of Q to be relatively high.

Also as I only performed the pre-layout simulation so no parasitics are included. From what you said, if I manual introduce some Resistance for the inductors and some paracitics (maybe anywhere in the circuit), the output swing should be decreased. Is that right? It looks I make everything too ideal causing the large swing. Is there any specific nodes, once parasitics appear, that make the performance very parasitic sensitive?

smlogan said:

The range of DC values of the MOS drain and source will be less than in your present topology. As a result, setting the gate voltage to assure the switch is on or off may be easier.

Thanks for you nice structure, I did see that the resultant structure results in a better performance. That is, getting close to the ideal case regardless of the fact of large output swing. Thanks!!!

But I want to try one more thing to make the current structure more usable. That is, I want to measure how much impedance introduced since I have replaced the ideal switches with  MOSFET switches. (Like measure the C_equivalent between Voutp and Voutn). The basic ideas is to do a AC analysis and measure the Voltage/Current. And then acquire the imaginary part of the impedance. I am presenting the adopted equations I tried in the output setup or in the ADE calculator. None of them work.

1. imag(value((VF("/net1")-VF("/net2"))/IF("/I0/M1/G") 1e3 ))

2. imag(value(VF("/net1")-VF("/net2") 1e3) /value(IF("/I0/M1/G") 1e3 ) )

Did I make some mistake on calculating the impedance?

Thanks,

Alex

Dear Alex,

>  if I manual introduce some Resistance for the inductors and some
> paracitics (maybe anywhere in the circuit), the output swing should
> be decreased. Is that right?

Yes. I believe the added parasitic elements will reduce the magnitude of the sustaining amplifier's negative resistance and hence the steady-state oscillation amplitude relative to the amplitude you are now observing.

>  Is there any specific nodes, once parasitics appear, that make the
> performance very parasitic sensitive?

I think you will gain more insight if you experiment with the location and sensitivities of added parasitics than if I suggest specific nodes and circuit traces. Hopefully, you will agree.

>  I am presenting the adopted equations I tried in the output setup
> or in the ADE calculator. None of them work.

I can only guess what "net1" and "net2" are - and perhaps /I0/M1/G is the gate current of the MOS switch? I am not sure what impedances you are trying to measure. Perhaps the expressions are not working if you have not saved the gate current and hence it returns "nil"?

In my first response, i added that it might be best to use a separate test circuit to study the small and large signal impedances of your MOS switch. In the test bench, I would bias the MOS device as it will be biased in the VCO. You can use an ideal inductor of large value to make the impedance to any DC source you use for biasing very large relative to the impedance you are trying to measure. Apply an ideal current source to the node(s) that you want to measure the impedance and then perform a large or small signal sinusoidal analysis. The resulting impedance can be measured by taking the ratio of the voltage waveform  across the current source divided by the waveform of the applied current. The ratio will be a function of frequency and will have real and complex parts. Hence, you can study the real and imaginary equivalent impedances at any specific frequency using the value() function for a specific frequency of interest. For a small signal analysis, you can set the amplitude of the current source to 1 with 0 phase and the resulting voltage will have the units of ohms. You will not need to take the ratio.

I hope this helps Alex. Perhaps Andrew sees a syntax error with your expressions that I overlooked. He is far more skilled at quickly catching syntax errors than I!

Shawn

smlogan said:

>  I am presenting the adopted equations I tried in the output setup
> or in the ADE calculator. None of them work.

Like Shawn, it's not clear to me what you're actually doing here.

Andrew.

Shawn,

smlogan said:

Perhaps the expressions are not working if you have not saved the gate current and hence it returns "nil"?

You are right, when I saved the node current it worked for me.

But I am still confusing with several points that pointed by you. I will attach the testbench schematic and the resultant impedance along with the assignment of different fields of 'AC Isin' and R, L values. In such case you can easily see if I was doing right or wrong and can provide clear direction based on the schematic and settings.

OK, in order to estimate of the small signal negative resistance characteristic, I may want to do the AC analysis and look at the impedance across the sustaining MOSFET.

1. For the sustaining MOSFET, were you referring to the M5 & M6?

2. In order to do the AC Analysis to get the impedance, I may need to add a AC current source between the nodes of Vsupply+ and Voutn (maybe or Voutp). Then set Ind. to be large enough like 1mH. Are the  testbench and settings correct?

3. I tried to do as in 2. with the result shown as follows. I am wondering what is the negative resistance you were referring to?

smlogan said:

The magnitude of the negative resistance must exceed the magnitude of the real part of your inductance at the desired frequency of oscillation to both ensure oscillator start-up and steady-state oscillation. 

As I have wiki-ed the definition of the negative resistance. It is a property of some electrical circuits and devices in which an increase in voltage across the device's terminals results in a decrease in electric current through it. But I am confused with the meaning in your context. Are you meaning (a) the Real part of the acquired Impedance, which is -6.408m as shown. Or the other case (b), the negative resistance, which I do not know what it is now, should be over than what I got from the real part (-6.408m) of the impedance (you said inductance as quoted, probably it is impedance)  from AC analysis.  Which case is the correct understanding?

4. I believe what I did is a large signal AC analysis which is the only AC analysis from the 'Analyses' Menu of the ADE panel. What do you mean by small signal AC analysis? Is it a DC analysis? As far as I know, the DC analysis is performed based on a biased DC operating point with a small AC variation applied on. Or just if I apply a very small amplitude of current source, the AC signal is small enough to be called "small singal AC analysis" in your words?

Thanks,

Alex

Dear Alex,

> 1. For the sustaining MOSFET, were you referring to the M5 & M6?

No. The sustaining amplifier is the oscillatior amplifier. An explanation with a graphical view is provided at:

http://community.cadence.com/cadence_technology_forums/f/33/t/30853

In your case, place an ideal current source between voutp and voutn.

> 3. I tried to do as in 2. with the result shown as follows. I am wondering

> what is the negative resistance you were referring to?

Please refer to the description in the URL.

> 4. I believe what I did is a large signal AC analysis which is the only AC

> analysis from the 'Analyses' Menu of the ADE panel. What do you mean by small

> signal AC analysis? 

The AC analysis in the ADE-L panel of analysis finds the DC operating point and does a small-signal analysis about that point.

Shawn