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simulating node capacitance charging

yefJ

Hello , i am trying to build an RF frequency D FlipFlop as shown bellow.

On the node Q signed by blue arrow i get a very abnormal charge and discharge behavior.

On the first TG opening Q charges half the way. When TG closes, it charge Q till the end although its not suppose to charge at all at this step(closed TG) ,as shown  in the last plot bellow.

Is there a way to see  how much capacitance we have on node Q when TG opens?

Thanks.



Parents

  • You could use the captab capability to report the instantaneous capacitance operating point info at the the times in question. The easiest way to do this is first to enable a dc analysis with the captab settings (strictly speaking it's not the DC analysis, but an info analysis, and so you could potentially use a row in the Save circuit information analysis table to add a new captab output - but for now I'll just showing doing it from dc). This is on the DC options form:

    Then on the transient options form, enable infotimes to be the times you want to output the capacitance info - and give the name of the captab info analysis (the name is generated automatically by checking the captab on the DC options above - the name I've given here is the name that appears in the netlist):

    Then after running the simulations, under Results->Print->Capacitance Table you'll get this - with a cyclic field at the top to pick the time you wish to look at:

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Hi Yefj,

    yefJ said:
     When TG closes, it charge Q till the end although its not suppose to charge at all at this step(closed TG) ,as shown  in the last plot bellow.

    I  added some labels to better explain my comment.

    If I understand your comment, and TG is the top most transmission gate, it appears TG1 (the bottom most transmission gate) operates on the complementary clock version of clk/clk_not. Hence, when TG assumes its high-impedance state, TG1 assumes its low impedance state and the charge on node Q serves to charge up your unlabeled gate node Q2. Hence, between the charge that flows to Q2 and the charge injection of opening and closing TG and TG1, it is expected that the node voltage of node Q will change.

    Does this make sense Yefj? You can minimize the change by added a signficant capacitor to node Q.

    Shawn

  • in reply to ShawnLogan

    Hello Shawn, i think to isolate the focus at Pass gate.

    is there an article  with Cadence virtuoso implementation where i cant see how to plan a TG that will get threw my data  when the clock rises?

    Thanks

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