output resistance test vs I_out(Vout) test

Dear robert21,

> 1.what is the effect of connecting Voltage source in series with current source?
> the current source will force a certain current , and the voltage source will
> force a voltage on the end of the current source?

Please consider what an ideal current source (defined as having an infinite output impedance) does. Its funciton is to set a DC current independent of what the voltages are its terminals. Hence, if you are trying to establish a voltage at the drain of the current source device, placing an ideal voltage source of any value at the positive terminal of the current source in your schematic will not impact the DC current of the ideal current source.

> 2.when we are testing output current we put on the output DC voltage source
> and sweeping it measuring the current.
> how adding another test voltage source not interfering with the behavior of the circuit?
> is there more passive way to measure the voltage and current on the output?

I think I outlined a method to do this in a reply to your posted question at:

community.cadence.com/.../test-signal-iprobe-rout-calculation

You mentioned that the method appeared to work. Is there a reason you cannot use the same methodology in your current example?

> 3.when measuring output resistance(output impedance) do we need to put 1V bias
> voltage in the Vdc source beyong the Vac 1uV amplitude?
> or we could test impedance with AC magnitude only?

Yes. If you do not, you are not controlling the drain voltage of your nmos_lv_3 device. The output impedance of an MOS device is well known to be a function of its drain-source voltage.

I hope these address your questions robert21,
Shawn

Dear robert21,

> 1.what is the effect of connecting Voltage source in series with current source?
> the current source will force a certain current , and the voltage source will
> force a voltage on the end of the current source?

Please consider what an ideal current source (defined as having an infinite output impedance) does. Its funciton is to set a DC current independent of what the voltages are its terminals. Hence, if you are trying to establish a voltage at the drain of the current source device, placing an ideal voltage source of any value at the positive terminal of the current source in your schematic will not impact the DC current of the ideal current source.

> 2.when we are testing output current we put on the output DC voltage source
> and sweeping it measuring the current.
> how adding another test voltage source not interfering with the behavior of the circuit?
> is there more passive way to measure the voltage and current on the output?

I think I outlined a method to do this in a reply to your posted question at:

community.cadence.com/.../test-signal-iprobe-rout-calculation

You mentioned that the method appeared to work. Is there a reason you cannot use the same methodology in your current example?

> 3.when measuring output resistance(output impedance) do we need to put 1V bias
> voltage in the Vdc source beyong the Vac 1uV amplitude?
> or we could test impedance with AC magnitude only?

Yes. If you do not, you are not controlling the drain voltage of your nmos_lv_3 device. The output impedance of an MOS device is well known to be a function of its drain-source voltage.

I hope these address your questions robert21,
Shawn

Hello Shawn, an Idial 10uA current source component  gives me a huge 1.4V drop. (as shown bellow)

Why in simulation i have such a voltage drop on ideal current source?
Thanks

Dear robert21,

robert 21 said:

Why in simulation i have such a voltage drop on ideal current source?
Than

The voltage drop  will always be vdd - vgs where vgs is the gate source voltage of your diode connected M0 device. As I think I mentioned in my last response robert21, an ideal current source will force the DC current and with an infinite output impedance can support any voltage at its terminals. Its lower potential terminal voltage is set by the gate-source voltage of your diode connected device M0 at a current of 10 uA. The upper terminal is set by whatever voltage you have assigned node vdd - in your example 1.8 V.

Is my answer any clearer to you this time?

Shawn

Hello Shawn why the voltage drop over the current source cant be zero,

so we will see 1.8V an 10uA on the output of the idial current source?

Thanks.

DIdn't Shawn just explain that? Why would it be zero? The voltage is defined by the diode-connected transistor with 10um flowing through it, not by a voltage set by the current source itself (since a current source does not set a voltage...). This is pretty basic electronics...

Andrew.

Hello Andrew, If i understand it correctly the output voltage cannot be 1.8V because the Drain voltage of the NMOS has to such that it supports 10uA going threw it

so the voltage Source is irrelevant in this case?

it will produce the voltage based on the current going threw it?

correct?

Dear robert21,

robert 21 said:

Hello Andrew, If i understand it correctly the output voltage cannot be 1.8V because the Drain voltage of the NMOS has to such that it supports 10uA going threw it

Andrew is correct and your understanding is now correct too!

robert 21 said:

so the voltage Source is irrelevant in this case?

As I think I noted, the current source, since it has an infinite output impedance, will force the 10 uA current independent of the voltage at its terminals. Hence, the DC voltage to which you set node vdd does not impact the DC voltage across the gate-source junction of your diode connected device M0.

robert 21 said:

it will produce the voltage based on the current going threw it?

The MOS diode connected device M0 gate-source voltage is defined by its drain source current per the constitutive equations governing it.

Shawn

Thank you very much