sampled pnoise on multi-phase switched cap circuit

Hi jfyan,

A quick note.   Here's an article on sampleratio (you must have access to Cadence Online Support):

How to use the field "Sample Ratio" in pnoise type "sampled(jitter)" 

These are general Switched Capacitor filter articles

Measuring Noise in a Switched Capacitor Filter 

How to reconcile the linear noise, pnoise, and transient noise results on a switched capacitor ckt? 

best regards,

Tawna

thanks, Tawna,

I set sampleratio = 2 in noisetype = timedomain, is there any difference?  

regards

jeff

thanks, Tawna,

I set sampleratio = 2 in noisetype = timedomain, is there any difference?  

regards

jeff

Hi Jeff,

What version of software are you using?    In virtuoso IC617ISR17, IC618, or ICADVM20.1 with Spectre 17.1ISR2 or later, 18.1, 19.1, 20.1 21.1, there are two noise types:   timeaverage and sampled(jitter).

noisetype=timedomain is pretty old (more than 5 years old).  See the article below:

How to use Pnoise Sampled analysis in Spectre (versions 18.1, 19.1, 20.1, 21.1) 

best regards,

Tawna

Hi Tawna,

we are using Version 19.1.0.237.isr3.

and here is my spectre script:

samplednoise pnoise start =100 stop=200k dec=50 pnoisemethod=fullspectrum
+noisetype=sampled measurement = [pm0] annotate = status sampleratio=1
pm0 jitterevent trigger = [clock_probe]
+triggerthresh = 0.5 triggernum=1 triggerdir = rise
+target = [vout 0]

it looks as i expected: the noise density lows by rt.2 if samplerration = 2 compared with 1 for white noise;

my following question is, I tried double the sampling freq. by using 2x clock on clock_probe while still keep sampleratio =1, I thought the result would be close to the case when sampleratio=2 and clock_probe=1x fund freq, but it is not. can you tell me why?  and which is the right one?

regards

jeff

Dear jfryan,

jfyan said:

my following question is, I tried doubling the pss. fund freq by using 2x clock on clock_probe while still keep sampleratio =1, I thought the result would be close to the case when sampleratio=2 and clock_probe=1x fund freq, but it is not. can you tell me why?  and which is the right one?

I did not see any details of your switched capacitor resistor noise test bench in your post, hence I do not know if you have included a lowpass filter on the resistor  noise. If you do not, or if the bandwidth of the lowpass filter is not sufficiently less than your value of fs/2, the resistor noise will be aliased. If so, the noise density you measure of the sampled noise will not be linear with sample frequency.

The impact of the sample frequency on the sampled output noise is discussed in the recent Forum post at URL:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/49080/could-anyone-explain-this-sampled-noise-simulation-result

I performed a number of simulations in response to the post and included a note at URL:

noise_figure_nose_figure_sampled_sml_081521.pdf

that details the simulation results, the test bench, and a graphical illustration of the impact of sampling frequency on the resistor noise. If I understand your question, this may be of some relevance as I do not know your circuit under study.

Anyway, this came to mind and wanted to pass it your way in case it provides any insight into your question.

Shawn

thanks Shawn,

It is very helpful to read through the thread you posted.the following is the simple circuit I try to sim. the noise using pnoise.

if RC << Ton, KT/C noise will be on the output, and noise density is sqrt (KT/C*2/fund), if you run pss, and pnoise. fund = fs 

 but, if you look at the circuit, the noise should be updated at 2fs = 2fund, so the noise density should be the same as the case where the sampling clock is 2fs.

so, I think it is proper to use sampleratio= 2. which is quite similar to the example of clock multiplier that Tiwna posted. 

my following question is, can I use clockprobe feature in noisetype = sampled, where the probe clock is 2fs freq?

I thought the above two cases should be close to each other on the noise result.  but, it looks not, 2x clock probe doesn't reduce the noise density by sqrt2.. do you know why? 

thanks a lot for your help.

regards

jeff

First, I want to thank Shawn for stepping in and answering questions on the forum.   I appreciate you!  

Jeff, for in-depth technical questions, I suggest filing a Case on https://support.cadence.com .   There's actually an entire team of AEs who assist Cadence customers on technical questions like this  :-) 

(The Cadence AEs answering questions on this forum typically do so in their spare time: evenings, lunch hour, breaks, etc.)  

best regards,

Tawna

What does your PSS analysis look like?  (this is important).  When using sampled(jitter) pnoise, the pnoise stop freq should be 1/2 the pssfund (assuming there is no divider in the circuit.  If there is a divider, the pnoise stop freq is 1/2 the freq of the net being measured.  The pnoise start freq is say 4 decades below that).   Sampleratio is used for frequency divider circuits.   It is the ratio between sampled frequency and fundamental frequency.  See the Article that I mentioned earlier for an example.

To simulate switch capacitor circuits, there are certain things that must be done to get accurate results.  They are outlined in the links in my earlier response.   Sorry, I don't have time to dig into this more.  Please contact https://support.cadence.com for assistance.

best regards,

Tawna

Dear jfryan,

jfyan said:

the following is the simple circuit I try to sim. the noise using pnoise.

if RC << Ton, KT/C noise will be on the output, and noise density is sqrt (KT/C*2/fund), if you run pss, and pnoise. fund = fs 

 but, if you look at the circuit, the noise should be updated at 2fs = 2fund, so the noise density should be the same as the case where the sampling clock is 2fs.

Your question regarding the noise density being "doubled" when there are two parallel switches with non-overlapping control signals relative to the case with a single switch puzzled me. I did not expect this intuitively when I studied your circuit topology. Hence, as my time allowed over the past week or so, I performed a number transient noise simulations using a circuit that I believe represents the circuit topology you illustrated in your most recent post Jeff. Perhaps I have not captured it correctly - and my sincere apologies if I did not!!

I conducted a number of experiments to examine the resulting integrated noise on the load capacitor node - as well as the noise on the node prior to the switches adjacent the noisy resistor. I varied combinations of the following:

1. Switch type: no switches enabled (i.e.., direct connection between resistor and load capacitor), single switch enabled, two parallel switches enabled with non-overlapping control signals

2. Fixed 1K noisy resistor with load capacitances of 1 pf, 10 pf, and 100 pf corresponding to bandwidths of much greater than the switches operating frequency of 10 MHz, close to the sampling frequency, and far less than the sampling frequency

3. Number of dft points used in the subsequent analysis of the transient noise simulation data using the single switch circuit topology to determine the required number of points to provide sufficient accuracy of the integrated transient noise voltage

I compared the resulting integrated noise for the "no switch" case (i.e., direct connection between resistor and load capacitor)  to that provided by the theoretical value for the corresponding noise bandwidth and found the two values correlate well.

The analyses indicate that for the case where the -3 dB bandwidth of the lowpass filter formed by the noisy 1 K resistor and the load capacitor is far less than the sampling frequency divided by two, the use of two parallel switches provides an integrated noise equivalent to the integrated voltage noise for a single switch circuit topology. This result seems to differ from your expectations, but does tend to be consistent with my initial intuition. Once again, Jeff, perhaps my assumptions about your circuit topologies or your fundamental intentions are incorrect. However, I did want to follow up with you with my experiments and observations. If you have the patience, and this is still of interest to you, I did place a Portable Document Formatted file detailing my test bench (basically your switch topologies and resistor/load capacitor), motivation, graphical and tabular summaries of the simulation data (Fourier analyses of voltage noise of both circuit nodes) and my conclusions at URL:

ent.box.com/.../epe7cskp6habzk4yrt2nc945q95iwn3a

The URL will expire at the end of 2021. If you do care to review it and have any thoughts, comments, or observations you wish to share, please feel free! If it is no longer of interest or your time does not allow, that is absolutely fine too!

Shawn

hi Shawn,

thank you a lot for your time and help here.

I don't I presented my question very well. what I want to ask is how to simulate a switched cap circuit with multiphase clocks. 

one example is I shown previously, in which the output noise is updated at 2*fund, so the noise from the input should be the same with one switch running at fs = 2fund. using pss+pnoise can't directly give me an answer. so sampleratio might be an option here. 

another method is transient noise simulation that I think you're trying to do in your doc.

page 29 and page 32 looks answer my question, what I care is the noise density for this two cases, I think, on page 29, the double side noise density from the calculation should be sqrt(kT/C/10MHz), while on page 32, the double side noise density be sqrt(kT/C/20MHz). i don't understand what is vres_sampled rms voltage noise =47.6 uV/root Hz? or just 47.6uV for rms noise ?

thanks again

jeff 

Dear jfryan

jfyan said:

i don't understand what is vres_sampled rms voltage noise =47.6 uV/root Hz? or just 47.6uV for rms noise ?

As shown in Figure 1 from page 6 (the test bench), vres_sampled is the net at the output of the two switches. I included simulation cases where both switches were closed for the entire duration (i.e., no sampling occurs), one switch is active at a 10 MHz rate with a 25% duty cycle during which the switch is closed (see example waveforms on page 9) and the two parallel switches are both active each with non-overlapping duty cycles of 25% (example waveforms on page 10). 

Since this is a sampled system at 10 MHz when the switches are operating, the noise is only worth evaluating over 1/2 the switching frequency of 10 MHz or 5 MHz. Hence, I integrated the noise between 100 kHz and 5 MHz to determine the integrated voltage noise in uV for many cases. For the cases where the load capacitor is 100 pf (the only case where the RC -3 dB frequency is much less than the Nyquist frequency of 5 MHz and hence the aliasing is minimal), whether there are no switches active, one switch active or two switches active, the integrated noise is about the same (see the tabular summary on page 35).

I hope this clarifies some answers to your questions....In summary, I don't believe the noise density is difference between the case where one switch only is active or if two parallel switches are active based on these transient noise simulation results. It sounds as if you still don't agree.

Shawn

Figure 1

(from page 6 of URL: ent.box.com/.../epe7cskp6habzk4yrt2nc945q95iwn3a

hi Shawn,

thanks.

so, what is DFT plot, is it noise density or noise power over freq?

I'm keeping asking about the noise density difference between the two cases, not noise power. noise power is always KT/C :)

Regards,

Jeff