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  3. sampled pnoise on multi-phase switched cap circuit

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sampled pnoise on multi-phase switched cap circuit

jfyan
jfyan over 3 years ago

Hi,
I have one question about the sampled pnoise simulation:
If I have a switched capacitor sample and hold circuit to sample the noise of resistor R, and now I add another switch sampler just paralleled with the first switch, with same sampling freq (fs) but nonoverlapping. so, the pss fund. freq = fs, but essentially the switch freq is 2fs.

how can  I simulate the circuit to get the right noise density (4kTR*pi/2*f3db/fs), instead of 4kTR*pi/2*f3db*2/fs? is pnoise option "sampleratio" is right way to do here.

thanks
Jeff

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  • ShawnLogan
    ShawnLogan over 3 years ago

    Dear jfyan,

    jfyan said:
    If I have a switched capacitor sample and hold circuit to sample the noise of resistor R, and now I add another switch sampler just paralleled with the first switch, with same sampling freq (fs) but nonoverlapping. so, the pss fund. freq = fs, but essentially the switch freq is 2fs.

    I do not believe your switch frequency is 2fs with the introduction of a second parallel switch whose phase only differs from the first parallel switch. The switch frequencies, and hence pss analysis, is still at fs and not at 2fs.

    Shawn

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  • jfyan
    jfyan over 3 years ago in reply to ShawnLogan

    Hi Shawn

    yes, that is the problem, the pss fund. freq can only be set at fs, not 2fs. but essentially the resistor noise is updated at two fs. here, for example, these two clocks are 25% duty cycle, and half 1/fs away from each other.

    regards,

    Jeff  

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  • Tawna
    Tawna over 3 years ago

    Hi jfyan,

    A quick note.   Here's an article on sampleratio (you must have access to Cadence Online Support):

    How to use the field "Sample Ratio" in pnoise type "sampled(jitter)" 

    These are general Switched Capacitor filter articles

    Measuring Noise in a Switched Capacitor Filter 

    How to reconcile the linear noise, pnoise, and transient noise results on a switched capacitor ckt? 

    best regards,

    Tawna

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  • jfyan
    jfyan over 3 years ago in reply to Tawna

    thanks, Tawna,

    I set sampleratio = 2 in noisetype = timedomain, is there any difference?  

    regards

    jeff

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  • Tawna
    Tawna over 3 years ago in reply to jfyan

    Hi Jeff,

    What version of software are you using?    In virtuoso IC617ISR17, IC618, or ICADVM20.1 with Spectre 17.1ISR2 or later, 18.1, 19.1, 20.1 21.1, there are two noise types:   timeaverage and sampled(jitter).

    noisetype=timedomain is pretty old (more than 5 years old).  See the article below:

    How to use Pnoise Sampled analysis in Spectre (versions 18.1, 19.1, 20.1, 21.1) 

    best regards,

    Tawna

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  • jfyan
    jfyan over 3 years ago in reply to Tawna

    Hi Tawna,

    we are using Version 19.1.0.237.isr3.

    and here is my spectre script:

    samplednoise pnoise start =100 stop=200k dec=50 pnoisemethod=fullspectrum
    +noisetype=sampled measurement = [pm0] annotate = status sampleratio=1
    pm0 jitterevent trigger = [clock_probe]
    +triggerthresh = 0.5 triggernum=1 triggerdir = rise
    +target = [vout 0]

    it looks as i expected: the noise density lows by rt.2 if samplerration = 2 compared with 1 for white noise;

    my following question is, I tried double the sampling freq. by using 2x clock on clock_probe while still keep sampleratio =1, I thought the result would be close to the case when sampleratio=2 and clock_probe=1x fund freq, but it is not. can you tell me why?  and which is the right one?

    regards

    jeff

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  • ShawnLogan
    ShawnLogan over 3 years ago in reply to jfyan

    Dear jfryan,

    jfyan said:
    my following question is, I tried doubling the pss. fund freq by using 2x clock on clock_probe while still keep sampleratio =1, I thought the result would be close to the case when sampleratio=2 and clock_probe=1x fund freq, but it is not. can you tell me why?  and which is the right one?

    I did not see any details of your switched capacitor resistor noise test bench in your post, hence I do not know if you have included a lowpass filter on the resistor  noise. If you do not, or if the bandwidth of the lowpass filter is not sufficiently less than your value of fs/2, the resistor noise will be aliased. If so, the noise density you measure of the sampled noise will not be linear with sample frequency.

    The impact of the sample frequency on the sampled output noise is discussed in the recent Forum post at URL:

    https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/49080/could-anyone-explain-this-sampled-noise-simulation-result

    I performed a number of simulations in response to the post and included a note at URL:

    noise_figure_nose_figure_sampled_sml_081521.pdf

    that details the simulation results, the test bench, and a graphical illustration of the impact of sampling frequency on the resistor noise. If I understand your question, this may be of some relevance as I do not know your circuit under study.

    Anyway, this came to mind and wanted to pass it your way in case it provides any insight into your question.

    Shawn

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  • jfyan
    jfyan over 3 years ago in reply to ShawnLogan

    thanks Shawn,

    It is very helpful to read through the thread you posted.the following is the simple circuit I try to sim. the noise using pnoise.

    if RC << Ton, KT/C noise will be on the output, and noise density is sqrt (KT/C*2/fund), if you run pss, and pnoise. fund = fs 

     but, if you look at the circuit, the noise should be updated at 2fs = 2fund, so the noise density should be the same as the case where the sampling clock is 2fs.

    so, I think it is proper to use sampleratio= 2. which is quite similar to the example of clock multiplier that Tiwna posted. 

    my following question is, can I use clockprobe feature in noisetype = sampled, where the probe clock is 2fs freq?

    I thought the above two cases should be close to each other on the noise result.  but, it looks not, 2x clock probe doesn't reduce the noise density by sqrt2.. do you know why? 

    thanks a lot for your help.

    regards

    jeff

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  • Tawna
    Tawna over 3 years ago in reply to jfyan

    First, I want to thank Shawn for stepping in and answering questions on the forum.   I appreciate you!  

    Jeff, for in-depth technical questions, I suggest filing a Case on https://support.cadence.com .   There's actually an entire team of AEs who assist Cadence customers on technical questions like this  :-) 

    (The Cadence AEs answering questions on this forum typically do so in their spare time: evenings, lunch hour, breaks, etc.)  

    best regards,

    Tawna

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  • Tawna
    Tawna over 3 years ago in reply to jfyan

    What does your PSS analysis look like?  (this is important).  When using sampled(jitter) pnoise, the pnoise stop freq should be 1/2 the pssfund (assuming there is no divider in the circuit.  If there is a divider, the pnoise stop freq is 1/2 the freq of the net being measured.  The pnoise start freq is say 4 decades below that).   Sampleratio is used for frequency divider circuits.   It is the ratio between sampled frequency and fundamental frequency.  See the Article that I mentioned earlier for an example.

    To simulate switch capacitor circuits, there are certain things that must be done to get accurate results.  They are outlined in the links in my earlier response.   Sorry, I don't have time to dig into this more.  Please contact https://support.cadence.com for assistance.

    best regards,

    Tawna

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