Using Ideal Frequency Divider Block in Cadence

Hi astroshey,

In general, we don't recommend using SpectreRF for PLLs.   (For the full text, see Article  20468264: How should I simulate my PLL circuit in SpectreRF? https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000679z2UAA   (Note:  You must have a login for the Cadence Support site.  You can request one on the Support main page.  If you are a University student, you'll need to talk to the Professor who manages your Cadence account.)

Why?

• PLL circuits are notoriously difficult to get convergence with in Spectre RF. All signals in the circuit must be periodic, and the circuit must respond periodically; otherwise, you will not get convergence. One example is described in Article 20134975  PSS not converging on PLL circuit.
• Simulating PLL circuits are typically best accomplished with transient and transient noise analysis.

Cadence recommends using the method presented in the PLL Verification (Using ADE Explorer and XCELIUM) Rapid Adoption Kit​

You may also want to look at the Virtuoso Transient Noise Appnotes:

• Spectre Transient Noise Simulation from ADE - Advanced 
• Spectre Transient Noise Simulation from ADE – An Introduction
• You could also use an event-like behavioral simulation of an overall PLL, as in the methodology described in Ken Kundert's paper Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers,​ Ken Kundert Designer’s Guide Consulting, Inc.  Jitter measurements can be directly inserted into the type of macromodels used in that paper. Usually, the extracted metric in this type of methodology is the sampled jitter (pmjitter) and it is used directly. The Designer’s Guide is an excellent website (http://www.designers-guide.org/Analysis/) which has a section on phase noise and jitter, which you may find helpful.

If you want to simulate part of the PLL (say the oscillator with a divider circuit) I recommend:

Article (20491924)
Title: How to set up pss/pnoise sampled(jitter) when simulating a driven circuit or a VCO, both containing dividers
URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009xzDeEAI&pageName=ArticleContent

best regards,

Tawna

Hi Tawna, 

I am looking into getting access to Cadence Support so that I can read through the material you shared. However, my PLL loop does converge in a reasonable amount of time (~2-3hrs). I am using hb and hbnoise analysis which have been recommended to me by my professors. Would you recommend any other analysis for PLL loop simulation, specially for phase noise? BTW I was successfully able to simulate VCO and divider blocks together, I am now focusing on loop phase noise. Thank you for your help! 

Dear astroshey,

astroshey said:

I see that for the BW you went with one-twentieth of the reference frequency which equals 5MHz. I went with one-tenth, so my loop BW is 10MHz. From then on I got C1=134p, C2=0.2*C1=26.8p, and Rp=500 Ohm using the zeta and wn formulas. My Kvco=2*pi*10G, my Ip=15mA (I am not certain if I calculated this correctly, it seems too large to me) and the divide ratio is 1000.

I examined your loop parameters, and given your other loop parameters, a charge pump current of 15 mA is a factor of 10 too large to produce a small-signal bandwidth of about 10 MHz.  Hence, I chose a charge pump current of 1.5 mA to perform the small and large signal simulations.

I have updated the note at URL:

www.dropbox.com/s/hg2o6c1wk8lirfj/ss_ls_pll_pfd_100g_vco_100meg_ref_031423v1p1.pdf?dl=0

to include the small and large signal transfer functions. The peaking in the transfer function does result in some ringing in the phase response. I've illustrated it for one of the simulations showing the input and output phase  in Figure 1.

astroshey said:

and the divide ratio is 1000. I would appreciate any further insights you have based on the information I provided,

Andrew Beckett said:

The comments at the top of the model in the VerilogA view suggest that it's hard to get this to work with big divide ratios (I would agree - it's using a titrating capacitor approach). I think you'd need the tt parameter to be much smaller.

I forgot to mention in my initial response that a possible way to avoid the large divider ratio is to cascade two of the verilog-A divider instances each of which has a divide ratio of 10. However, one parameter that your divider may not be accurately modeling is the delay of the divider. The divider delay will impact loop stability (i.e. jitter peaking and transient response). If you know the approximate delay of your transistor level divider, it may be worth including this delay in your transient simulation.

astroshey said:

Would you recommend any other analysis for PLL loop simulation, specially for phase noise?

I will not pretend to comment on your question for Tawna nor for Andrew!

However, we recently did have a Forum post where this topic was discussed, and there are several opinions provided. The Forum post is at URL:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/55593/observing-pll-phase-noise-with-hbnoise/1388668#1388668

Shawn

Figure 1

Hi Shawn, 

Thank you for the additional analysis and suggestions! You mean I can cascade three divide by 10 frequency dividers to get a divide ratio of 1000, instead using 1 divide by 1000 verilogA block? Also, as per your suggestion, I changed the value of Ip, and now I am getting a better phase noise but still it's not quite reasonable yet. Please see attached. I am still working on improving it, if I could get it to -70dBc/Hz at 1MHz offset that would be good for now. In my transistor-based charge pump, where should I pay close attention to besides the loop filter in order to get a narrow bandwidth? Thank you!

Dear atroshey,

astroshey said:

ou mean I can cascade three divide by 10 frequency dividers to get a divide ratio of 1000, instead using 1 divide by 1000 verilogA block?

I was not clear and apologize! Yes, I was proposing that you replace the single verilog-A block whose divider setting is 1000 to, for example, 2 cascaded verilog-A blocks with respective divider settings of 10 and 100. Of course, you could also cascade three verilog-A divider blocks with each of the three set having divider settings of 10. The basic thought is to use much smaller divider settings in the block to avoid the limitation the code presents for a large divide ratio.

astroshey said:

I changed the value of Ip, and now I am getting a better phase noise but still it's not quite reasonable yet. Please see attached.

With the charge pump current of 15 mA, or with your updated value of 1.5 mA, did you look at the transient response of your loop? If you saved the initial transient of your pss simulation, you might examine its loop response. I did not find the 15 mA charge pump current as unstable from a small-signal perspective, but the loop bandwidth was about 44 MHz and the peaking was over 8 dB. I was concerned about its large signal transient response.

I don't know what kind of a VCO you are using. You did note its phase noise was -100 dBc/ Hz bu did not include the offset frequency for that measurement. I don't see any evidence of its phase noise in your plot. I also do not know the noise of your 100 MHz iinput reference clock - which also plays a role in the output phase noise.

In summary, your phase noise plot does not look right for a few reasons. If you examine the phase noise of the large simulation I ran where the input noise has a 100 MHz bandwidth and the phase-locked loop bandwidth is 10 MHz on page 10 (Figure 10) at URL:

www.dropbox.com/s/hg2o6c1wk8lirfj/ss_ls_pll_pfd_100g_vco_100meg_ref_031423v1p1.pdf?dl=0

you will note the output phase noise starts to drop off rapidly for offset frequencies greater than 10 MHz.

To better illustrate a few major concerns, I updated the note to include an annotated version of your Forum phase noise plot above with my concerns on page 15. On page 16, I included the measured output phase noise of a phase-lock loop and indicate the salient features that are missing from your simulated phase noise plot.

I think it might be worth stepping back to make sure your phase-locked loop is showing the transient response you expect, has a reasonable static phase offset in steady-state, and has a settling time commensurate with the time chosen to start the pss analysis. Perhaps a few conventional transient simulations might be chosen to validate the expected performance prior to performing additional pss/pnoise analyses? These are all my opinions only!

Shawn

Dear astroshey,

My response was flagged as spam and will hopefully be released soon in order that you might read over my comments.

Shawn

HI Astroshey,

Transient noise.  

If you are able to simulate a PLL with spectreRF, count yourself lucky.   Typically, they won't converge.

If you are simulating dividers with SpectreRF, you need to look at Article 20491924: How to set up pss/pnoise sampled(jitter) when simulating a driven circuit or a VCO, both containing dividers.   This is a NEED.   I'm writing an appNote with R&D that discusses this (currently in review) and many other aspects of pnoise.  Sorry I can't devote much time to answering your questions as much as I'd dearly love to do so.  My day job keeps me busy late into the night.

There are a ton of useful SpectreRF articles and best practices on https://support.cadence.com .  When you get access, ping me and I'll point you to them so you can download them.

best regards,

Tawna

Hi Shawn, 

Thank you very much for all your insight and support on this! I appreciate all the time you spent on it. I will follow your suggestion of stepping back and looking at the transient simulations of the circuit. I just have one last concern for now. I get this warning message (see attached screenshot, the yellow highlighted portion). Does this mean that there is a possibility that my solution does not fully converge and this lack of complete convergence results in degraded phase noise? And using Transient Noise analysis (as Tawna suggested) could resolve this issue? BTW, I am not sure if my cadence version (version IC6.1.8-64b.500.14) has transient noise analysis option. Thanks again for all your time and efforts!

best regards~

Dear astroshey,

You are most welcome, but I am just trying to provide a thought or two. I know how frustrating it can be!

astroshey said:

I will follow your suggestion of stepping back and looking at the transient simulations of the circuit.

I think your effort will be well worth it. I know it may seem to be delaying you from getting your desired result, but the fact that your current phase noise result appears so unusual suggests something is amiss with the pss solution. I am glad you are doing this!

astroshey said:

I just have one last concern for now. I get this warning message (see attached screenshot, the yellow highlighted portion). Does this mean that there is a possibility that my solution does not fully converge and this lack of complete convergence results in degraded phase noise?

Certainly the warning message is not expected and does indicate the convergence process is abnormal. However, I was more surprised to observe that the pnoise analysis is using a 700 MHz signal!

I looked back in your Forum post and see you have specified a relative harmonic of 7! I thought the output frequency of your phase-locked loop (i.e. input to the PFD) was 100 MHz?  You noted your feedback divider was 1000 and with a 100 GHz VCO, that suggests only a 100 MHz output frequency is available. Hence, the relative harmonic should be set to 1.

Is my understanding correct astroshey?

astroshey said:

And using Transient Noise analysis (as Tawna suggested) could resolve this issue? BTW, I am not sure if my cadence version (version IC6.1.8-64b.500.14) has transient noise analysis option.

Transient noise is definitely an option, but does introduce some additional processing that is, what I will term, non-trivial. Specifically, you will need to perform a Fourier analysis of your output waveform that requires some specific settings to provide a good phase noise estimate.

My personal thought - and this is my thought only - is that you consider running a few transient simulations to validate the loop is behaving as you expect. If all looks well, make any adjustments to the pss settings (for example, allowing a longer stabilization time if required), change the relative harmonic to 1 if you are attempting to simulate the phase noise of a 100 MHz output, and re-run a pss analysis following by a pnoise analysis. You can compare the pss transient waveform (the converged solution) and make sure it looks close to your transient only simulation to assure yourself the pss solution is reasonable.

However, please use your best judgement as you know your circuit and the time you have available!!

Shawn

Hi Shawn, 

Thank you for pointing that out. I must have overlooked it! I just changed it to 1. Thank you for giving me the debugging tips! I am on it. Instead of using pss and pnoise, I am using hb and hbnoise (shouldn't be any difference, right?). Again, thank you for your support! You definitely made this time easier for me!

PS: I just wanted to share my PPL performance with you. I think it looks good. I will proceed with changing relative harmonic to 1 and increasing the tstab, and rerun the simulations. Thank you~

Best regards~

If the simulation setups are done properly (this is key), you should get the same answer with shooting pss and harmonic balance.  For strongly nonlinear circuits, shooting will be faster.  For nearly linear circuits, hb will be faster.  

If you have circuits with fast rise times (think square waves and more nonlinear), we recommend using pss-shooting (pss).  It's faster.  hb would take many harmonics (slow) - if you don't have enough harmonics, your answer will be incorrect.

If your waveform shapes are more "sinusoidalish", then use harmonic balance (hb).  It's going to be faster.

It's a matter of using the right tool for the job.  You can use a hammer to pound a screw into a wall, but really the proper tool is a screwdriver.  Similarly, you can use a screwdriver to pound a nail into a wall, but it's pretty darned inefficient.  A hammer is the better tool.  Same thing with pss shooting vs hb.  Use the right tool for the job. 

There is an appnote that I recommend having your professor download for you: Getting the Most Out of Spectre® X-RF 21.1: Maximizing Performance .   It discusses when it's appropriate to use Shooting pss vs hb. If you have dividers in your circuit, you need to use pss shooting (not hb).   

There are many articles on https://support.cadence.com that discuss topics like this.  I hope you're making headway with your professor to be able to download some of our valuable "best practices" articles.  It'll save you much time and help with your understanding.

best regards,

Tawna

If you are going to use transient noise, you really want to read the appnotes on this topic. Setup is so important to get accurate results. 

You can look in the spectre hierarchy for some good workshops (you don't need to download anything from https://support.cadence.com .  They are located here: <SPECTRE21.1>/tools.lnx86/spectre/examples/SpectreRF_workshop/spectrerf_workshop_21.1.tar.gz.  You need to copy spectrerf_workshop_21.1.tar.gz to a location where you have write permission.

gunzip spectrerf_workshop_21.1.tar.gz 

tar xf spectrerf_workshop_21.1.tar

And look inside for: 

• SpectreRF APS Workshop for Full Spectrum Shooting  Pnoise spectreRF_fullspectrum.pdf
• SpectreRF APS Workshop for HBnoise Timeaverage and Transient Noise Correlation spectreRF_hbnoise_tranNoise_correlation.pdf
• SpectreRF APS Workshop for Pnoise Sampled and Transient Noise Correlation spectreRF_pnoise_sampled_tranNoise_correlation.pdf
• SpectreRF APS Workshop for Ring Oscillators    spectreRF_ring_oscillator.pdf
• SpectreRF APS Workshop for Transient Noise Calibration   spectreRF_tranNoise_calibration.pdf
• SpectreRF APS Workshop for Wireless Simulation   spectreRF_wireless.pdf
• Instructions for downloading and installing the GPDK for the above workshops   gpdk_download_install.pdf   

All are very good.  (By the way, there's more good stuff like this listed in Article:  SpectreRF Application Notes and Tutorials - One of our best kept secrets! )

best regards, 

Tawna

If you are going to use transient noise, you really want to read the appnotes on this topic. Setup is so important to get accurate results. 

You can look in the spectre hierarchy for some good workshops (you don't need to download anything from https://support.cadence.com .  They are located here: <SPECTRE21.1>/tools.lnx86/spectre/examples/SpectreRF_workshop/spectrerf_workshop_21.1.tar.gz.  You need to copy spectrerf_workshop_21.1.tar.gz to a location where you have write permission.

gunzip spectrerf_workshop_21.1.tar.gz 

tar xf spectrerf_workshop_21.1.tar

And look inside for: 

• SpectreRF APS Workshop for Full Spectrum Shooting  Pnoise spectreRF_fullspectrum.pdf
• SpectreRF APS Workshop for HBnoise Timeaverage and Transient Noise Correlation spectreRF_hbnoise_tranNoise_correlation.pdf
• SpectreRF APS Workshop for Pnoise Sampled and Transient Noise Correlation spectreRF_pnoise_sampled_tranNoise_correlation.pdf
• SpectreRF APS Workshop for Ring Oscillators    spectreRF_ring_oscillator.pdf
• SpectreRF APS Workshop for Transient Noise Calibration   spectreRF_tranNoise_calibration.pdf
• SpectreRF APS Workshop for Wireless Simulation   spectreRF_wireless.pdf
• Instructions for downloading and installing the GPDK for the above workshops   gpdk_download_install.pdf   

All are very good.  (By the way, there's more good stuff like this listed in Article:  SpectreRF Application Notes and Tutorials - One of our best kept secrets! )

best regards, 

Tawna