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  3. What areas of OrCAD Capture would users like to see improved...

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What areas of OrCAD Capture would users like to see improved?

dfernseb
dfernseb over 2 years ago

OrCAD Capture is a powerful schematic capture solution used by many commercial and educational institutions. Its longevity and functional flexibility has made it a staple to PCB, Packaging, and FPGA design flows. As we continue to enhance the core product based on our strategic initiatives I'd like to get feedback from the users of where you feel we could provide the most value to accelerate your productivity. Is it in technology areas like library development, data management, simulation, etc... or in modernization of presentation, usability, and ecosystem?

I look forward to the dialog! Slight smile

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  • RFinley
    RFinley over 2 years ago

    Engineers like to complain about CIS.  I've used Orcad and occasional DxDesigner/Viewdraw since the late 80's so it takes a lot to bug me. 

    Need a way to define the page sequences in intelligent PDF exports to Acrobat distiller.  PDF pages don't follow the Capture project manager sequence.

    Most important:  resolving and preventing duplicate designators could be easier.   Have to compile a netlist to find them then search for them.   Would be nice if you could flag conflicts while annotating unassigned designators.  When engineers do the "annotate reset designators to ?" and re-sequence, I have to make them start over and redo their changes to the released DSN of the previous board release. 

    "Update Part Instance UI" for Part Manager.  Thank you for highlighting the property mismatch.   Any chance you could pop open a window and show me the schematic page where that part is located?   

    It took years to get engineers to stop taking a CIS-derived passive instance and changing just the value without re-linking the part.  Some very smart RF Engineers hate that no-loading parts is a two step process.   We can't set a part to Not-Present directly on the schematic page.  I goad my engineers to put them in a STUFF or NOSTUFF group, then go to part manager, select all the parts in the No-Stuff group, set Not-Present.  If they create new ways to avoid this two-step process, they don't accept how PART_NUMBER mistakes lead to corrupt BOM exports.  They cross their arms and look angry after showing them Variant View Mode, again.

    Please consider adding something similar to Variant View, except instead of showing Stuffing status, add a piece of text to each symbol for the group(s) the parts are assigned in.

    Occasionally engrs complain I won't let them buy licenses for Viewdraw/DxDesigner as it supports multiple orientations with property locations saved (to prevent overlapping text.)  We show value, voltage rating, package size, composition, tolerance on capacitors to address BOM mistakes.   Engineers waste layout schedule going full "Martha Stewart" on their schematics to resolve overlapping text with rotation. 

    But, please don't break the current DSN format that works all the way back to 16.x.  Someone here has to retire before I can float our old workflow to the center of a pond and set fire to it.   Their translator was written for 16.3 and can't read the 17.x padstack change.

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  • dfernseb
    dfernseb over 2 years ago in reply to RFinley

    @RFinley - Great feedback and some of these I believe are low hanging fruit. Please see my questions and comments below:

    I'll speak with development about:

    • PDF page sequencing and see if we can add an option to follow project sequence
    • Flagging duplicate designator on placement
    • Update part instance seems we need to support cross probe navigation
    • Setting a Not-present part directly in the schematic as a one step process
    1. In terms of adding a graphic to each part to visually indicate the group they belong in - I assume you are referring to component groups?
    2. For the "Martha Stewart" engineers is the ask here to support the same text orientation locations DxDesigner supports? I believe DxDesigner supports nine orientation points.
    3. No plans to change the DSN format as its been in circulation for a long time. One of the things OrCAD user love is the backwards compatibility of the design format.
    4. Have you filed any of these issues with support?

    Thanks again for sharing and I look forward to other user inputs!

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  • RFinley
    RFinley over 2 years ago

    I believe there's a timesaver/DRC function that could leverage the UI behind Variant View.   

    One thing that corrupts netlists:  adding more than one net alias on a net and engineering misses the conflict.  

    How about a view that highlights duplicate/conflicting net aliases and duplicate designators?  

     

    Love the find dialog panel introduced with 17.4.

    It's easy to show the session log.  Frustrating to see the dialog for find results.  Have to resize the DRC results dialog height to get find to show up.

     

    Another goof is editing a sub-block of a hierarchical project and forgetting to do a synch-up.   

    Warning message the next time a project is opened?   Out of date hierarchy?

    Third goof is engineers keep losing work when the Save button doesn't do a full save.  Page is open.  I have to tell engineers to quit out of Capture, then do a SVN commit to be sure everything is written to disk.

    We noticed an issue with CIS Update part properties.   We show the Temp Coefficient property to avoid mistakes.  But, not all CIS parts in the database use that property.   CIS Update Parts repeatedly can't accept a null field between the schematic instance and CIS data.  Do we click to update all?   That is the question.

    I found an issue with ::capDesignUtil::replaceAlias that acts the same from 16.6 to 17.4.   If multiple alias search string lengths don't match, replacement happens randomly, like it's triggering the replacement even though the string lengths don't match.  I found this out for a utility I shared: 

    https://community.cadence.com/cadence_technology_forums/pcb-design/f/pcb-editor-skill/51803/skill-method-to-optimize-netlist-pin-assignments-during-routing-using-allegro-orcad

    The TEMP- aliases intended to be replaced by real aliases must be of the same string length or random things happen when running the Tcl script.

    Thanks! 

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  • jgregoire
    jgregoire over 2 years ago

    Most of the Capture options have incredibly unhelpful names/descriptions. Some of them do unpredictable and catastrophic things.

    Symbol Editor is crusty and slow. Quality of life is horrible if you want to place a ton of pins while keeping both hands on the keyboard.

    Let me mass rename net aliases in the properties window!

    Make tabs, window docking, etc. remembered per-user, rather than saving it to the .opj file. That way I don't have to change it back every time someone else edits a design. Maybe just give me a global preference for where I want project windows to dock by default?

    Allow non-integer values for Zoom Factor. 2 is too much, and 1 disables zoom. Why can't I set 1.5?

    When placing a CIS part, I should be able to select which Manufacturer Part and Distributor Part I want! I don't want to have to print 6 alternate part columns just to get the part I want to export to the BOM.

    In Symbol editor, let me define default text locations for 0 degree and 90 degree rotation. That way every time I rotate a resistor, I don't have to fix the text locations.

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  • IWashburn
    IWashburn over 2 years ago

    Make it easier to update the symbol or footprint of a CIS part already in a schematic with an alternate symbol or footprint. Currently this has to be done through Part Manager -> Link Database Part. Lots of clicks and menus are required to get there, it would be nice if this option was embedded into the schematic editor itself (perhaps let me choose an alternate symbol/footprint from within the Property Editor which opens when I double-click the component in the schematic?)

    Let me turn off auto-naming of power nets from symbol power pin names. Currently I get hundreds of ERC warnings and markers indicating that a power net has multiple aliases just because it is connected to numerous symbols which use different names for their power pins. Having to sift through these hundreds of warnings just to make sure there isn't a legitimate one where two unrelated aliases are assigned to the same net is extremely tedious and time-consuming. 

    When placing pins in the schematic symbol editor, let me renumber/rename them on-the-fly without having to restart the Place Pin tool. Same with placing net aliases - I do not want to have to restart the Place Alias tool every time just so I can change the name of the alias.

    Let me copy and paste net aliases.

    Make the search scope more obvious in the Find panel - maybe add option to select Search Entire Project or Search Active Document. Having to carefully select the correct document in the project tree prior to executing a search is prone to error.

    Make Selection Filter dockable.

    When synchronizing up to a top-level hierarchical block when new ports have been added downstream, use up all blank space before displaying error that there is no more room in the sheet symbol. For example, if I have a large sheet symbol with four ports (one in each corner), but the linked sheet has five ports, when I use the "Synchronize Up" command I get an error saying "Unable to Add all ports/pins". This is due to lack of space, according to the Session Log. However, there is plenty of white space around the edges of the sheet symbol to add the one additional port. 

    Somehow indicate if a sheet in a hierarchy has been updated but is out-of-sync with the top hierarchical block.

    Prevent numerous unnecessary files from being written in the project directory every time I open or save a Capture project. I do not use Pspice, but every time I open a DSN or OPJ file I get a series of PSpice-related files and folders popping up in my directory. This can lead to severe cluttering. Similarly, every time I save a Capture file a PNG appears in the project directory showing just a small snippet of the schematic. I have no clue what its purpose is and it only adds to the clutter.

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