What areas of OrCAD Capture would users like to see improved?

I believe there's a timesaver/DRC function that could leverage the UI behind Variant View.   

One thing that corrupts netlists:  adding more than one net alias on a net and engineering misses the conflict.  

How about a view that highlights duplicate/conflicting net aliases and duplicate designators?  

Love the find dialog panel introduced with 17.4.

It's easy to show the session log.  Frustrating to see the dialog for find results.  Have to resize the DRC results dialog height to get find to show up.

Another goof is editing a sub-block of a hierarchical project and forgetting to do a synch-up.   

Warning message the next time a project is opened?   Out of date hierarchy?

Third goof is engineers keep losing work when the Save button doesn't do a full save.  Page is open.  I have to tell engineers to quit out of Capture, then do a SVN commit to be sure everything is written to disk.

We noticed an issue with CIS Update part properties.   We show the Temp Coefficient property to avoid mistakes.  But, not all CIS parts in the database use that property.   CIS Update Parts repeatedly can't accept a null field between the schematic instance and CIS data.  Do we click to update all?   That is the question.

I found an issue with ::capDesignUtil::replaceAlias that acts the same from 16.6 to 17.4.   If multiple alias search string lengths don't match, replacement happens randomly, like it's triggering the replacement even though the string lengths don't match.  I found this out for a utility I shared: 

https://community.cadence.com/cadence_technology_forums/pcb-design/f/pcb-editor-skill/51803/skill-method-to-optimize-netlist-pin-assignments-during-routing-using-allegro-orcad

The TEMP- aliases intended to be replaced by real aliases must be of the same string length or random things happen when running the Tcl script.

Thanks! 

I believe there's a timesaver/DRC function that could leverage the UI behind Variant View.   

One thing that corrupts netlists:  adding more than one net alias on a net and engineering misses the conflict.  

How about a view that highlights duplicate/conflicting net aliases and duplicate designators?  

Love the find dialog panel introduced with 17.4.

It's easy to show the session log.  Frustrating to see the dialog for find results.  Have to resize the DRC results dialog height to get find to show up.

Another goof is editing a sub-block of a hierarchical project and forgetting to do a synch-up.   

Warning message the next time a project is opened?   Out of date hierarchy?

Third goof is engineers keep losing work when the Save button doesn't do a full save.  Page is open.  I have to tell engineers to quit out of Capture, then do a SVN commit to be sure everything is written to disk.

We noticed an issue with CIS Update part properties.   We show the Temp Coefficient property to avoid mistakes.  But, not all CIS parts in the database use that property.   CIS Update Parts repeatedly can't accept a null field between the schematic instance and CIS data.  Do we click to update all?   That is the question.

I found an issue with ::capDesignUtil::replaceAlias that acts the same from 16.6 to 17.4.   If multiple alias search string lengths don't match, replacement happens randomly, like it's triggering the replacement even though the string lengths don't match.  I found this out for a utility I shared: 

https://community.cadence.com/cadence_technology_forums/pcb-design/f/pcb-editor-skill/51803/skill-method-to-optimize-netlist-pin-assignments-during-routing-using-allegro-orcad

The TEMP- aliases intended to be replaced by real aliases must be of the same string length or random things happen when running the Tcl script.

Thanks!