Match Track Lengths Across Multiple Layers

Sound like you wish to match length between components pin and not full net?

So you have to create pin pairs and constraint pin pairs instead of net.

Net exemple:

U1.1 U2.3 U4.11

second net

U1.2 U2.5 U4.6 R55.1

if you want to match U1.1 to U2.3 with U1.2 to U2.5 you have to create two pins pairs with theses points and then put them into a matchgroup,, not the nets

I appreciate the responses, no, i need full length.

I have simple pin-to-pin connections like U1.1 to R263.1, U1.5 to R302.1, U1.56 to R402.1, and so on. These are sequential IC signals, and due to space constraints and the use of SMD components with vias, the tracks change layers.

My goal is to match the track length on each layer, not just the total length. Since these signals need to be driven in a timely manner to enable or disable as required, it's crucial that the track length is consistent on each layer to control the signal timing properly.

I've tried using "Total Length" and "Relative Propagation Delay Length," but they don't give the desired results because they calculate the entire length across all layers, not per layer.

I’ve attached a simple image showing the connections, where U1 is the source, R* is the receiver, and the vias are represented as circles. The different colours represent different layers.

Does enabling Z delay solve you issue? So it take into account the length between layers.

Or your problem is different propagation delay on different layers ? On outer layers the speed is a little faster than inner layers. If so, do not constraint length but delay.

I do not think it is possible (maybe, but not easy: never have such case; maybe with a skill routine ) to match length per layer

Or your problem is different propagation delay on different layers ? On outer layers the speed is a little faster than inner layers. If so, do not constraint length but delay. 

That’s exactly what I need.
If you have any ideas, shortcuts, techniques or skill that could assist in resolving this issue, please share. In the meantime, I will explore enabling the Z delay to see if it helps.

thanks a lot

Or your problem is different propagation delay on different layers ? On outer layers the speed is a little faster than inner layers. If so, do not constraint length but delay. 

That’s exactly what I need.
If you have any ideas, shortcuts, techniques or skill that could assist in resolving this issue, please share. In the meantime, I will explore enabling the Z delay to see if it helps.

thanks a lot

So you have to constraint the delay using ns or ps insteat of length (mm or mils): doing so if your stackup is correctly defined it will solve your problem; Z delay enabled take into account the delay in via introduced by layer change.

Be aslo aware of pin delay if applicable in your case

See Steve note:

 https://community.cadence.com/cadence_technology_forums/pcb-design/f/pcb-design/46689/propagation-delay-delta-tolerance-value-in-mils