• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Allegro X PCB Editor
  3. Display Your Know How: Decoupling Capacitor

Stats

  • Replies 10
  • Subscribers 160
  • Views 2567
  • Members are here 0
More Content

Display Your Know How: Decoupling Capacitor

PCBTech
PCBTech 5 months ago

The golden rule of decoupling capacitor placement is to minimize the distance between the IC’s voltage pin and the capacitor.

What about the routing of the capacitor to POWER and GROUND pins/planes!!

Which among the above decoupling capacitor routing configurations is better?

Any improvements that can be done?

Simply answer by letter or include any reason to support your answer. Alternatives and opinions are welcome!

  • Sign in to reply
  • Cancel
  • JCTEYSSIER0
    JCTEYSSIER0 5 months ago

    None of these. Better may be like "C" but Power placed up to IX pin/right of capacitor pin.

    And depend aslo where the Ground pin of IC is located.

    This is for numeric IC. For analog one the answer differ. Problematic is not the same.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
  • excellon1
    excellon1 5 months ago

    Are these caps Mirrored as in on the bottom layer of the board under a BGA. ?

    If that's the case then Picture C looks the best.

    Best Regards,

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
  • PCBTech
    PCBTech 5 months ago in reply to JCTEYSSIER0

    Thanks for your insights, JCTEYSSIER0! I'd like to follow up on the placement of the Ground pin. Does its location have a significant impact on the decoupling capacitor routing?

    Additionally, how does the consideration change when designing an analog IC? Are there specific guidelines or best practices to keep in mind?

    I'd appreciate any thoughts or opinions on this matter, as it will help clarify the design considerations for Ground pin placement in both digital and analog contexts.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
  • PCBTech
    PCBTech 5 months ago in reply to excellon1

    That's correct, excellon1. The components are indeed placed underneath the IC, specifically on the bottom layer of the board.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
  • DavidJHutchins
    DavidJHutchins 5 months ago in reply to PCBTech

    I have had SI engineers request the the routing go from the pin to the cap then to the via:

    ...

    if I remember correctly they thought this reduces Ground Bounce type of issues

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
>
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information