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  3. Obtain all 'shorting' errors via skill

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Obtain all 'shorting' errors via skill

khuranav007
khuranav007 over 3 years ago

Hello,

Is there a way to filter 'shorting' errors from list of all DRCs in the design using Allegro Skill?  We short differently named nets together which leads to DRCs - is there a way to obtain a list of these errors (DRCs) as a result of shorting nets by the way of SKILL?  We do not add NET_SHORT property to suppress these DRCs.

Thanks!

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  • RFinley
    0 RFinley over 3 years ago

    Will this help?

    community.cadence.com/.../skill-method-to-optimize-netlist-pin-assignments-during-routing-using-allegro-orcad

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  • khuranav007
    0 khuranav007 over 3 years ago in reply to RFinley

    I don't know how this will help.

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  • khuranav007
    0 khuranav007 over 3 years ago in reply to RFinley

    I don't know how this will help.

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  • RFinley
    0 RFinley over 3 years ago in reply to khuranav007

    I need to re-write my description as this process is layout driven or it won't be useful. 

    I was using the skill "find" command to iterate through all pad-to-pad DRCs, extract the associated net names, and write a back annotation file provided one of the two nets associated has a "TEMP" prefix.  Otherwise, skip.

    In order for this to work, you need to add temporary single pin pads to nets in the schematic to go to layout and cause DRC errors.   

    The end-result is driven by placing these temp pads to cause intentional shorts.  An annotated schematic with updated net-aliases to make connections for clean, optimized routing is the intended result.

    Wanted to save you hours of time searching for the secret method of reading netnames from a DRC error instance as this is something SKILL iLS training and the rest of their support website is strangely silent on, finding the net name associated with... anything.

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