• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      oldmouldy
      oldmouldy 60 Points
    • 2
      MZ20250602835
      MZ20250602835 45 Points
    • 3
      steve
      steve 40 Points
    • 4
      RJ202412171240
      RJ202412171240 25 Points
    • 5
      JohnFr38
      JohnFr38 20 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,868 Points
    • 2
      oldmouldy
      oldmouldy 11,060 Points
    • 3
      eDave
      eDave 7,596 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,226 Points
    • 5
      redwire
      redwire 5,138 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    Best way to do blind/buried RF vias?

    Category: Allegro X PCB Editor

    By jayk314

    •

    updated over 5 years ago by Duc Nguyen SV

    10 replies • 5552 views
  • Discussion

    Text on Manufacturing/Properties layer

    Category: PCB Design

    By OLY29

    •

    updated over 5 years ago by Dale Peterson

    1 replies • 1447 views
  • Discussion

    Drill table Creation in allegro 17.2

    Category: Allegro X PCB Editor

    By jayukacha

    •

    updated over 5 years ago by Dale Peterson

    6 replies • 19814 views
  • Discussion

    XNET not generated when too many connections.

    Category: PCB Design

    By Michael Ford

    •

    updated over 5 years ago by Michael Ford

    1 replies • 14117 views
  • Discussion

    Change to active layer when using Show-Measure?

    Category: PCB Design

    By avant

    •

    started over 5 years ago

    0 replies • 12972 views
  • Discussion

    PSpice models for heterogeneous schematic symbols

    Category: PCB Design

    By Bogga

    •

    started over 5 years ago

    0 replies • 13351 views
  • Not Answered

    Change NetName

    Category: Allegro X Capture CIS

    By honey1

    •

    updated over 5 years ago by Klaustrafob

    4 replies • 18318 views
  • Discussion

    How to add a large amount of text individually in Allegro.

    Category: Allegro X PCB Editor

    By Woojin24

    •

    updated over 5 years ago by avant

    2 replies • 14337 views
  • Discussion

    Problems added new Alias to Wire

    Category: PCB Design

    By Klaustrafob

    •

    started over 5 years ago

    0 replies • 4842 views
  • Discussion

    orcad get pin location

    Category: PCB Design

    By tennywhy

    •

    started over 5 years ago

    0 replies • 13642 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information