• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      CF202606104231
      CF202606104231 45 Points
    • 2
      Electro Node
      Electro Node 40 Points
    • 3
      avant
      avant 30 Points
    • 4
      excellon1
      excellon1 21 Points
    • 5
      Siri
      Siri 20 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,533 Points
    • 2
      oldmouldy
      oldmouldy 10,680 Points
    • 3
      eDave
      eDave 7,286 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,231 Points
    • 5
      redwire
      redwire 4,238 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    Hierarchical design default pin placements

    Category: PCB Design

    By algoldst

    •

    updated over 7 years ago by oldmouldy

    1 replies • 14973 views
  • Discussion

    Wrong data for extracted fields

    Category: PCB Design

    By jpeley

    •

    started over 7 years ago

    0 replies • 13786 views
  • Discussion

    Suppress unconnected internal pads;legacy artwork (in Pad Editor) get checked automatically after replaced padstack through skill

    Category: Allegro X Scripting - Skill

    By kaykay0929

    •

    started over 7 years ago

    0 replies • 1809 views
  • Discussion

    Starting a Batch or a Script file out of a Skill Porgramm

    Category: Allegro X Scripting - Skill

    By Mathis

    •

    updated over 7 years ago by Mathis

    1 replies • 10211 views
  • Discussion

    pin swapping on a large bga in HDL

    Category: PCB Design

    By stumpsr1019

    •

    updated over 7 years ago by redwire

    1 replies • 14712 views
  • Discussion

    Unable to define via structure

    Category: PCB Design

    By GK MN

    •

    updated over 7 years ago by LouShay

    1 replies • 15320 views
  • Discussion

    Drill Legend Table error

    Category: PCB Design

    By KKSP

    •

    updated over 7 years ago by steve

    1 replies • 14328 views
  • Discussion

    Via symbol visuality

    Category: PCB Design

    By KobiC

    •

    updated over 7 years ago by KobiC

    5 replies • 17067 views
  • Discussion

    Orcad EDM tool for Allegro Pcb Editor

    Category: PCB Design

    By HSID

    •

    updated over 7 years ago by RFinley

    1 replies • 14881 views
  • Discussion

    How to Export PCB data out in *.PAR, *.NEC from OrCAD 16.6?

    Category: PCB Design

    By HEM PUSHP

    •

    updated over 7 years ago by steve

    5 replies • 18686 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information