• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Site
  • Community Search
  • User
Forum - Thread List
  • Discussion

    Production-Standard General-Use Microcontrollers? Locked

    13243 views
    3 replies
    Latest over 6 years ago
    by JonnyJobin
  • Discussion

    route keepin Locked

    14973 views
    1 reply
    Latest over 6 years ago
    by oldmouldy
  • Discussion

    Changing Line Width of a Trace in a Net without DRC Errors Locked

    23541 views
    16 replies
    Latest over 6 years ago
    by TC2019
  • Discussion

    Attaching shapes to components

    9878 views
    3 replies
    Latest over 6 years ago
    by Andak
  • Discussion

    Dynamics to attach a circle to the cursor during active command

    12376 views
    0 replies
    Started over 6 years ago
    by Andak
  • Discussion

    find filter control Locked

    15969 views
    9 replies
    Latest over 6 years ago
    by Dale Peterson
  • Discussion

    Update net names and net groups in an existing design Locked

    15173 views
    1 reply
    Latest over 6 years ago
    by oldmouldy
  • Discussion

    Regarding making of Layout from schematic in Allegro PCB Designer linux version 17.2? Locked

    15841 views
    9 replies
    Latest over 6 years ago
    by VijayKK
  • Discussion

    VIA selection for Automatic Router Locked

    13287 views
    4 replies
    Latest over 6 years ago
    by Magnetcore
  • Discussion

    Highligting symbols

    13852 views
    4 replies
    Latest over 6 years ago
    by vimaldevlpr
  • Discussion

    Need advice for product packaging

    13949 views
    1 reply
    Latest over 6 years ago
    by SiPguy
  • Discussion

    Netlist generation _Ocard -Allegro with diferent reference designator) Locked

    1135 views
    2 replies
    Latest over 6 years ago
    by edd506
  • Discussion

    Planar Spiral Inductor Design Process Locked

    28289 views
    17 replies
    Latest over 6 years ago
    by excellon1
  • Discussion

    Replace Blind Via with Blind/Buried Stacked Via? Locked

    5623 views
    6 replies
    Latest over 6 years ago
    by Tmills
  • Discussion

    Creating Netlist Error Locked

    12944 views
    0 replies
    Started over 6 years ago
    by Jeff Sanmina
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information