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Discussion

Using ChipWare (CW) Components in Quartus FPGA Builds? Locked

4659 views

0 replies

Started over 1 year ago
by SL202501311657
Discussion

spiceIn using tsg files for symbol creation Locked

3585 views

1 reply

Latest over 1 year ago
by Andrew Beckett
Discussion

"Impact of Using Polygon Function Instead of Rectangle Function in Cadence PCELL" Locked

1601 views

4 replies

Latest over 1 year ago
by Andrew Beckett
Discussion

how to merge a list of pins back into bus<0:7> data<8:15> Locked

1242 views

2 replies

Latest over 1 year ago
by Andrew Beckett
Not Answered

The Host ID/Reference key you entered was not found in our system. 0

1448 views

0 replies

Started over 1 year ago
by ForrestGump
Discussion

Thermal Warpage Simulation in Celsius

1738 views

0 replies

Started over 1 year ago
by SimTech
Suggested Answer

Disable automatic screenshot Orcad Capture 0

3256 views

6 replies

Latest over 1 year ago
by edahub
Discussion

automatic Router using to route shortest path between two pin (IN virtuoso studio IC23.1) it is using in layout XL Locked

7041 views

11 replies

Latest over 1 year ago
by RobMan
Suggested Answer

Axlmeterupdate issue with macro 0

2731 views

4 replies

Latest over 1 year ago
by ABIKRISHNA
Suggested Answer

shape parameter +1

8441 views

7 replies

Latest over 1 year ago
by Elecguy
Discussion

Export Manufacturing Files

15668 views

3 replies

Latest over 1 year ago
by eDave
Discussion

How to Extract Real and Imaginary Parts of S11 from Port 1 in AWR?

2523 views

3 replies

Latest over 1 year ago
by Sabrina A
Discussion

Unable to remove text labels after flattening layout pcell Locked

4900 views

5 replies

Latest over 1 year ago
by Ma100B
Suggested Answer

fillet question +1

4622 views

4 replies

Latest over 1 year ago
by AsbjornEdvalds
Answered

Copying text from CIS Explorer tables 0

2828 views

7 replies

Latest over 1 year ago
by pertinax