• Discussion

  Create class or bus for nets

  13639 views
  2 replies
  Latest over 13 years ago
  by ChienVO
• Discussion

  Highlight location xy in rpt file

  17226 views
  8 replies
  Latest over 13 years ago
  by luanvn81
• Discussion

  Simulating verilog using cadence Locked

  14226 views
  1 reply
  Latest over 13 years ago
  by MTP3
• Discussion

  Testing valid shape Locked

  14586 views
  2 replies
  Latest over 13 years ago
  by psill
• Discussion

  (16.5+) Capture Symbol Editor Wish-list Locked

  13044 views
  2 replies
  Latest over 13 years ago
  by UlfK
• Discussion

  Vpulse and Vsource Locked

  23713 views
  5 replies
  Latest over 13 years ago
  by Andrew Beckett
• Discussion

  How do setup for net is with 50 ohm impedence Locked

  13162 views
  1 reply
  Latest over 13 years ago
  by kabalee
• Discussion

  change default GUI callback Locked

  22091 views
  17 replies
  Latest over 13 years ago
  by Leonid Y
• Discussion

  Signal enabling on same clock Locked

  13491 views
  0 replies
  Started over 13 years ago
  by Kirubha
• Discussion

  Packager error SPCODD-7 Locked

  14343 views
  4 replies
  Latest over 13 years ago
  by Jerry GenPart
• Discussion

  How to translate netlist with subcircuits into top-level subcircuit? Locked

  6612 views
  1 reply
  Latest over 13 years ago
  by skillUser
• Discussion

  How to avoid a group of cell from getting optimised Locked

  13876 views
  1 reply
  Latest over 13 years ago
  by fitz
• Discussion

  preserve module ports Locked

  14349 views
  1 reply
  Latest over 13 years ago
  by fitz
• Discussion

  change layout view Locked

  13408 views
  1 reply
  Latest over 13 years ago
  by Rik Lee
• Discussion

  HDL design and scald layout Locked

  12908 views
  0 replies
  Started over 13 years ago
  by jflmeggitt