• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    update the layout connectivity by shorting two terminals of Analog lib Resistor in layout Locked

    11231 views
    2 replies
    Latest over 3 years ago
    by naresh9005
  • Discussion

    I hope other nets will be opened and wiring will be done automatically. Is there a script or technique that fits this? Locked

    13513 views
    11 replies
    Latest over 3 years ago
    by Andrew Beckett
  • Not Answered

    This file was created by 6.x capture data format. 0

    8387 views
    2 replies
    Latest over 3 years ago
    by ajeeth palani
  • Discussion

    Wrong package height shown using IDF Export Locked

    9029 views
    0 replies
    Started over 3 years ago
    by jatins
  • Discussion

    Allegro NC Drill and NC Route Integer.decimal format not exported in Gerber

    16159 views
    13 replies
    Latest over 3 years ago
    by DavidJHutchins
  • Discussion

    How to set a funckey to submenu item in Allegro / PCB designer ?

    10468 views
    4 replies
    Latest over 3 years ago
    by nutron
  • Discussion

    COMBINED and variable definition syntax in cds.lib file Locked

    10294 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    How can I import verilog-A (.va) file in the cadence virtuoso? Locked

    10417 views
    1 reply
    Latest over 3 years ago
    by Andrew Beckett
  • Discussion

    How to check if signal top.moduleA.aaa is directly connected to top.moduleB.bbb using xcellium TCL? (or simvision) Locked

    10266 views
    1 reply
    Latest over 3 years ago
    by StephenH
  • Discussion

    How can I set the specific color feature with SKILL?

    5716 views
    2 replies
    Latest over 3 years ago
    by ichliebedich
  • Discussion

    sampled pnoise on multi-phase switched cap circuit Locked

    22318 views
    19 replies
    Latest over 3 years ago
    by FormerMember
  • Discussion

    PLL reference model for PSS+PNOISE Locked

    4110 views
    5 replies
    Latest over 3 years ago
    by FormerMember
  • Discussion

    Checks/Asserts export Locked

    2271 views
    2 replies
    Latest over 3 years ago
    by dragank
  • Discussion

    Maestro - use other output as spec value. Locked

    4468 views
    6 replies
    Latest over 3 years ago
    by JeyJey
  • Discussion

    How to plot current results along with last run results in the same window/tab in viva. Locked

    4246 views
    4 replies
    Latest over 3 years ago
    by kenc184
<>

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information