• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    Problem importing spice netlist Locked

    3188 views
    1 reply
    Latest 10 months ago
    by Andrew Beckett
  • Discussion

    Copy schematic/symbol views hierarchically Locked

    955 views
    2 replies
    Latest 10 months ago
    by Andrew Beckett
  • Not Answered

    Cadence Connect Hyderabad, India - Register for Futuristic Design Authoring for Integrated Signal, Power, and Thermal Design Session on Nov 25 0

    636 views
    0 replies
    Started 10 months ago
    by Renu Vibha
  • Not Answered

    Cadence Connect Hyderabad, India - Register for Futuristic Design Authoring for Integrated Signal, Power, and Thermal Design Session on Nov 25 0

    1306 views
    0 replies
    Started 10 months ago
    by Renu Vibha
  • Suggested Answer

    Defining Custom Shortcut Keys on OrCAD Capture CIS v17.2 0

    21199 views
    7 replies
    Latest 10 months ago
    by Bilal S
  • Discussion

    LoapPull Analysis For Differential Power Amplifier Locked

    3795 views
    2 replies
    Latest 10 months ago
    by RM202501276525
  • Discussion

    How to restrict net renaming to specific cell instances in layout using SKILL? Locked

    2642 views
    2 replies
    Latest 10 months ago
    by Andrew Beckett
  • Answered

    Export as STEP 0

    3936 views
    1 reply
    Latest 10 months ago
    by JuanCR
  • Discussion

    How to interpret a single backslash from an input file? Locked

    2876 views
    4 replies
    Latest 10 months ago
    by MM202511045434
  • Discussion

    How to create and run multiple simulations in Fidelity CFD using Python API

    1069 views
    0 replies
    Started 10 months ago
    by Gaurav
  • Answered

    How to open a .dsn file with tcl command? 0

    12259 views
    12 replies
    Latest 10 months ago
    by PatEscher
  • Discussion

    IP6514E Driver for Nand Flash Locked

    1859 views
    0 replies
    Started 10 months ago
    by XJ202511099616
  • Discussion

    Transfer design variable from schematic / layout to av_extracted view Locked

    2229 views
    2 replies
    Latest 10 months ago
    by Andrew Beckett
  • Discussion

    Explanation of stb analysis results YG, YL, ZG, and ZL Locked

    1822 views
    0 replies
    Started 10 months ago
    by Frank Wiedmann
  • Discussion

    Question on integrated noise in PNOISE (sampled) Noise summary Locked

    3001 views
    4 replies
    Latest 10 months ago
    by Yuto Lau
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information