• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List
  • Discussion

    create customized process design kit with skill code Locked

    2782 views
    1 reply
    Latest 9 months ago
    by RobMan
  • Suggested Answer

    Using SKILL to route differential pair 0

    1979 views
    2 replies
    Latest 9 months ago
    by In2p3SubRenard
  • Discussion

    Pcell inductor EMX simulation Locked

    3141 views
    0 replies
    Started 9 months ago
    by SamanMKD
  • Suggested Answer

    Automatic Wire Split on Component Placement 0

    1124 views
    1 reply
    Latest 9 months ago
    by TechnoBobby
  • Discussion

    Meet the Champion of the Month: August 2025

    2129 views
    1 reply
    Latest 9 months ago
    by geda
  • Suggested Answer

    Add Footprint Column to Place Part Window in Schematic Capture 0

    1102 views
    1 reply
    Latest 9 months ago
    by Jeet
  • Discussion

    Hi, How virtual clock latency is getting updated after Clock tree synthesis stage and what parameters does it consider to update that latency? Locked

    2975 views
    0 replies
    Started 9 months ago
    by MS202509109551
  • Discussion

    How to check and fix redundant vias in Allegro X APD?

    3257 views
    1 reply
    Latest 9 months ago
    by masamasa
  • Discussion

    new DRC rule(s) added to new(er) gpdk045 versions? Locked

    1815 views
    1 reply
    Latest 9 months ago
    by Andrew Beckett
  • Discussion

    Images of symbol view generated with hiGenerateThumbnails do no show text Locked

    10081 views
    8 replies
    Latest 9 months ago
    by Andrew Beckett
  • Not Answered

    OPEN JDK Resoucre 0

    7835 views
    2 replies
    Latest 9 months ago
    by CC20250910538
  • Discussion

    max usage of CPU cores in spectre/aps++ simulation Locked

    3104 views
    3 replies
    Latest 9 months ago
    by Andrew Beckett
  • Discussion

    Testable and testconstraint attribute supports in reg_verifier? Locked

    4128 views
    3 replies
    Latest 9 months ago
    by StephenH
  • Discussion

    Unavailability of Disk Space for Spectre Simulations Locked

    3887 views
    4 replies
    Latest 9 months ago
    by Andrew Beckett
  • Not Answered

    Hide the window after using command "exportNetList" in ASC 0

    1756 views
    2 replies
    Latest 9 months ago
    by Gelzone
<>

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information