• Discussion

  Open multiple calibre rve files in skill Locked

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  1 reply
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• Discussion

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  0 replies
  Started over 7 years ago
  by drdanmc
• Discussion

  AMS Netlister Error: "Illegal non-local reference to constant function [10.3.5(IEEE)]" Locked

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  0 replies
  Started over 7 years ago
  by Abel Ace
• Discussion

  How to retain the same impedance for a cline in both surface and inner layers Locked

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  5 replies
  Latest over 7 years ago
  by oldmouldy
• Discussion

  Multi-Voltage domain pin checks at schematic level Locked

  14272 views
  0 replies
  Started over 7 years ago
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• Discussion

  report_timing after clock tree synthesis shows the same clock to be ideal on capture flop while propagated on the launch flop Locked

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  3 replies
  Latest over 7 years ago
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• Discussion

  Suppress Errors While Automatically Exporting Padstack with Shape

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  Latest over 7 years ago
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• Discussion

  SDF back annotation in systemVerilog design using interfaces Locked

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  Started over 7 years ago
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• Discussion

  License Not working in user profile Locked

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  1 reply
  Latest over 7 years ago
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• Discussion

  Where can I ask tools question on Synopsys VCS simulator? Locked

  15041 views
  0 replies
  Started over 7 years ago
  by Ncsim User 1
• Discussion

  axlDBAddProp overwrite difference layer setting

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  5 replies
  Latest over 7 years ago
  by nightingale
• Discussion

  quickplace by schematic page number

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  5 replies
  Latest over 7 years ago
  by tennywhy
• Discussion

  Required Skill File For The 17.2

  9840 views
  3 replies
  Latest over 7 years ago
  by tennywhy
• Discussion

  display analog signal voltage in VerilogAMS Locked

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  2 replies
  Latest over 7 years ago
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• Discussion

  Hierarchical Design using characterized blocks timing issues Locked

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  Latest over 7 years ago
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