CDNLive India

CDNLive India took place last week. As usual, I made the long trip from California, nearly 30 hours door to door. There is aways something remarkable on these long flights and this time it was the WiFi pricing. It is nearly 50% more ($30.00 vs $21.99) for WiFi on the 5 hour San Francisco to Newark leg, than on the nearly 15 hour Newark to Delhi leg.

CDNLive India is organized differently from the other multi-day CDNLives in Silicon Valley and EMEA. Areas of interest are divided between the two days, so nobody comes both days. This is partly because over 2,000 people attend over the two days, and if they all stayed for both days then there isn't anywhere in Bangalore large enough to accommodate everyone. As it was, we were turning people away at the door since CDNLive was full to capacity. Jaswinder Ahuja, the President of Cadence India, welcomed everyone both days, pointing out that it was another record year, in both the number of papers submitted for possible presentation and in the number of people attending.

Another interesting aspect of nobody being there both days is that the opening keynote can be the same both days. Lip-Bu Tan delivered it on Thursday, and Anirudh Devgan on the Friday. It was the same presentation, but given the different backgrounds, the keynotes had different looks and feels. I think Madhavi will cover the keynote on The India Circuit blog.

Vinod Kariat

Vinod gave the Cadence technical keynote, titled AI Enabled Systems and the Analog Renaissance. Electronics in general and semiconductor in particular are at the centre of the next industrial revolution.

The highest visibility area is probably autonomous driving (ADAS), which is clearly coming even though the precise timescale remains a little murky. Vinod also pointed out that there are probably some tough problems in Indian traffic that you don't have on US freeways, such as all those rickshaws in the above picture.

Reliability is one of the biggest challenges in automotive, especially in the power and analog area. The target defect rate for automotive is zero. It turns out that 80-95% of field failures are in the analog portion. The high temperature for automotive is 170°C, which is a problem since many failures are caused by thermal overstress. In addition, aging of transistors is accelerated at higher temperatures, which makes it a challenge meeting the 15-20 year lifetime for automotive electronics.

Automotive is a huge challenge since we are building very reliable vehicles out of inherently unreliable semiconductor processes. A FIT is one failure per billion hours of operation. For a car we are looking for less than 10, but a semiconductor process is closer to 500 FITs.

During his talk, Vinod covered a lot of products that I have covered already this year. So I won't repeat everything her, just give you some links:

• VIrtuoso 2018, see Virtuoso 2018, a Fine Vintage
• Legato Reliability Solution, see Legato: Smooth Reliability for Automobiles
• Deep-learning driven analog design. See Cadence is MAGESTIC
• Virtuoso RF, which I am writing about but it hasn't appeared yet
• Quantus Smartview
• Low-power verification flow with Virtuoso Power Manager
• Liberate Trio, part of Cadence Cloud. See Liberate Trio: Characterization Suite in the Cloud

Subash Chandrar of Texas Instruments

The customer keynote on the first day was by Subash Chandrar of Texas Instruments, titled SoC Challenges and Opportunities in Automotive, Industrial, and IoT.

Subash started off looking at the megatrends driving the industry. Semiconductors are penetrating our daily lives in more and more ways, making the world healthier, safer, and more fun. Over the last 30 years the driving forces were compute centric, then mobile centric, then, today, data centric. He is much more optimistic than I am about IoT, even though he admits that it is very fragmented due to the differing requirements. I think the volumes for most products will be too low for this to be an SoC market, rather than board level (or maybe chiplet-level) integration.

Texas Instruments is very focused these days on markets with a high analog content. That is how they manage to be the most profitable semiconductor company at the moment. Three focus areas, which fit that description, are automotive, industrial, and IoT.

One area Subash called out in particular is what he called "wire replacement" in vehicles. The wiring harness in a modern car can weigh as much as 50kg (about 100 lbs) and that obviously has negative effects on performance and gas mileage. If many of those wires can be replaced with automotive Ethernet (on twisted pair) or even wireless, that is a big weight saving. Funnily enough he talked about many sensors in cars being connected by wires—but the first one he mentioned explicitly is tire pressure monitoring, which obviously cannot be done by wire (it would be a very twisted pair!).

One big driver in industrial is predictive maintenance. Nobody wants a machine to go down unexpectedly, much better to plan it. The big RoI is extending the operating life of equipment, since most industrial equipment operates in a harsh and unforgiving environment. Another challenge in all of these areas is that there will not be one standard for wireless networks. There are already dozens and that seems unlikely to change since they all have special characteristics that are ideal for some applications.

In automotive, we have bathtub curves that measure early mortality, and later after many years, aging. We need to get reliability down to a miniscule number. You chance of being hit by lightning (in your life, I assume) is a out 1 in 700,000. Automotive failure needs to be less likely than that.

Near the end, Subash turned to design and EDA. Increasingly, when I go to a keynote like this, it sounds a little as if the presenter has been indoctrinated by our system design enablement strategy. Increasingly, everything needs to be handled initially at the system level (for example, thermal analysis) and then pushed down into the details. Many constraints on the design, such as EM, power, reliability, or thermal, need to consider not just the whole chip, but the package, the board, and increasingly connectors, wiring and other stuff. The tools need to work seamlessly together.

Other Sessions

The rest of the day was taken up with parallel tracks. One that I thought was especially interesting was INVECAS, who develop a lot of GlobalFoundries' IP. This is perhaps more significant as a result of the announcement last week that GF would focus entirely on FD-SOI (and some other specialty processes like RF).

Mathworks (somehow, without my noticing, they renamed themselves from "The Mathworks") and Cadence gave a joint presentation on how you can use Matlab's advanced analysis tools to directly dig into the details of simulation results.

Watch for a post in a week or two on these two presentations. And later this week, I will write about day 2.

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