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If you live in California, as I do, then India is a long way away. It is 11½ hours time difference, for a start. Air India has a direct flight from San Francisco to New Delhi (over 16 hours) but since CDNLive is in Bangalore, that is not all that useful. As India is halfway around the world, it makes no difference if you go west or east. I have been to Bangalore via Singapore, and I have been to Bangalore via Frankfurt. The total time from entering San Francisco airport to leaving Bangalore airport is nearly 24 hours, with a couple of hours layover. The downside is that you land in Bangalore at 1:00am, so you don't get to your hotel until about 3:00am. The upside is that legendary Bangalore traffic is not too bad at 3:00am and it takes less than an hour to the hotel. The flights out of Bangalore are around 3:00am but at 11:00pm, the traffic is still bad so you need to allow a couple of hours to get to the airport.
CDNLive India takes place over two days but it is structured so that each day has a different focus. On Wednesday, August 28, there were tracks for Digital Implementation, Front-End Design, Digital Full Flow & Signoff, and two tracks for Custom/Analog Design—basically digital, analog, and mixed-signal design.
The day opened with three keynotes. The first was by Cadence President Anirudh Devgan. Obviously, the color was about the Indian market and Cadence in India, but to a first approximation, I covered this in my post CDNLive China 2019 and so I won't repeat it here.
The second keynote was by Cadence's Michael Jackson, who assured us he would not be moonwalking. He gave the technical keynote. Given the audience for the day, he focused on the increasing integration of the Genus and Innovus solutions, and on the Spectre X Simulator. These are the biggest recent developments in the Digital Full Flow, and in Analog/Mixed-Signal Verification.
I covered the deeper integration of the Genus and Innovus solutions, such as allowing synthesis restructuring to take place during place and route, in two posts about Chuck Alpert's talk at CDNLive Silicon Valley. (See Genus and Innovus: Together at Last and Genus and Innovus: Compus and iSpatial.) The bottom line is that using the Innovus solution for physical design gets much better results if you use the Genus solution for synthesis.
I covered a lot of the features of the Spectre X Simulator when we announced it at DAC earlier in the summer. (See my post Spectre X: Same Accuracy, New Speed.) The Spectre X Simulator gets the same results as previous versions of Spectre simulators but it has been completely re-architected to scale to large numbers of CPU in a data center or in the cloud.
The guest keynote was by Rituparna Mandal of MediaTek. She is both GM of MediaTek Bangalore and also Director of High-Performance CPU & Technology Group. She opened talking about Moore's Law (so insert your own Moore's Law graph here).
But she also had a version of Ray Kurzweil's graph of the growth of computing. The one above is Kurzweil's original. The amazing thing about this is that at first glance it looks like a Moore's Law graph about semiconductor scaling. But it actually starts with Babbage's Analytical Engine, goes through relays, to vacuum tube computation, discrete transistors, and only in that grey column on the right hand end of the graph is it about semiconductors. His point is that Moore's Law is just a phase of the general exponential growth in the power of computation, and just because Moore's Law applied to silicon scaling is slowing, that doesn't mean the increase in the power of computation will scale. Quantum computing? DNA computing? Who knows? The two horizontal lines are the power of a mouse brain and the power of the human brain. Today we are at about that mouse brain line.
Rituparna moved on to semiconductors and the recent challenges overcome and the future challenges to come. We have evolved transistors from planar, to FinFET, and are moving to gate-all-around (GAA) at 3/2nm. We finally have EUV. "We have driven designers mad with multi-patterning."
But recent processes have scaled using design technology co-optimization (DTCO) and now we are running out of tracks. She showed diagrams from imec very similar to the one in my posts Imec Roadmap and How Low Can You Go?. To keep going requires scaling boosters such as buried power rails, supervias, and self-aligned gate-contact (also sometimes called contact-over-active-gate). But we are running out of tracks. Obviously you can't have fewer than one P and one N transistor
The other huge challenge is resistance scaling. It has increased 3X node over node from 16nm to 7nm, and it will increase another 3X going from 7nm to 5nm. So we are "living on the edge, since what you see is never what you get, especially with the latest nodes."
Another big challenge is system complexity: power/performance tradeoffs, efficient power management, adaptive thermal management...but no tradeoff in SoC cycle time. With Moore's Law running out of steam, we are moving to Beyond Moore. The picture shows miniaturization on one scale and diversification on the other. Moore's Law and More than Moore.
This is all leading to a device explosion. In the mainframe era, we had many people sharing one device; in the PC and mobile eras, it was 1:1; and now in IoT, it is many devices per person.
Rituparna talked about AI and the story of AlphaGo and AlphaZero. I covered this story already in Deep Blue, AlphaGo, and AlphaZero and AlphaZero: Four Hours to World Class from a Standing Start.
But AI is having a major effect on EDA. Today, we have a design flow something like on the left, with all those green loopback arrows being a human designer reworking things. Her dream is more like the right-hand side, with a dashboard for chip design where you can change the frequency, change the routing, and it is adaptable to help you make the right choices.
Since this fits in with Anirudh's earlier keynote, where, among many other things, he talked about AI outside and no-human-in-the-loop design, she is clearly pushing on an open door.
On Thursday, August 29, there were tracks for Advanced Verification Methodology, Performance/Smart Bug Hunting, Emulation/Prototyping, and PCB Design—basically verification and PCB. I'll cover that next week.
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