DesignCon 2022: The 224G Show

13 Apr 2022 • 5 minute read

At DesignCon, there is often a theme that comes through, and this year there were two: silicon photonics and 224G SerDes. I already covered the opening keynote in my post The Convergence of Photonic and Electronic ICs. Today, it is the turn of 224G.

Let's start with 112G (just to point out the obvious, 224 is twice 112), which I covered in my posts:

The most important thing to know about 112G is that it uses PAM4 signaling, with two bits per clock, giving you an eye diagram like the one you can see in the image above. In my April fools day post, The All-Purpose EDA Keynote, I suggested "Moore’s law…blah, blah, blah. Show generic Moore’s law slide." Well, any presentation about high-speed SerDes can pretty much start off with "Growth in datacenter data...blah, blah, blah. Show a generic data growth slide".

Instead of focusing on the growing amount of bandwidth required, I'll show the importance by showing a slide of design starts (date from IPnest). This came from Wendy Wu's presentation The Future of 224G Serial Links on the last day of DesignCon. Most of the rest of this post is based on her presentation.

224G standards timeline As you can see from the above timeline, the 224G standardization process is just getting started and will last for at least a couple of years. If history is any guide, once the major parameters of the standard have been defined, companies like Cadence will build testchips. Waiting for the standard to be fully defined is just too late. People doing SoC designs need SerDes IP early in their design cycle.

As you can see from the above table, (right-hand column) much remains to be defined. We are a long way from building a testchip when the modulation approach has yet to be finalized! Even where it says "1m copper cable" that might have to be increased to 2m, despite the challenges, since with a 1m cable you cannot get from a server to a top-of-rack router. By the way, if you don't know what "FEC" stands for, then see my post What the FEC is Forward Error Correction?

The two main candidates for the modulation approach are PAM4 and PAM6. PAM4 is the same approach as is used for 112G and so the main question is whether it can be made to work with an acceptable bit-error-rate (BER) and insertion loss.

One of the tutorials on the first day of DesignCon was a group of engineers from AMD. When the host introduced Jeff Zhang, he did a double-take when reading the biography that stated, "he joined AMD in February 2022.". Jeff pointed out that that was the day the Xilinx acquisition closed, and most of what he was going to present was work done at Xilinx.

PAM4 takes two bits per transition (technically per Baud but people tend to incorrectly use Baud to mean bits per second). This is because log2(4) is 2. PAM8 takes 3 bits per transition since log2(8) is 3. This doesn't work for PAM6 since log2(6) is 2.584963, which is not a number anyone can work with. But it is close enough to 2.5 that we can construct the modulation so that 2½ bits are transmitted per transition. But that doesn't work on a per transition basis. In the same way that weird musical key signatures are often thought of as two simpler ones (for example, 5/4 times is sometimes counted as 1,2,3,1,2), two successive transfers can be handled differently so that they average out to 2.5 by transmitting PAM4 on the odd transfers, and PAM8 on the even transfers. That gives 2 bits and 3 bits, so it averages to 2.5 as required. Jeff detailed various options for doing this, but that's beyond this blog post (which is another way to say I didn't write them down).

LR is long reach. MR is medium reach. C2C is chip to chip. C2M is chip to module. XSR is extremely short reach. D2D is die-to-die. NPO is near package optics (this one is new for 224G). As a general rule, the longer the amount of copper, the more challenging it is to implement. The long reach case at the top has the cable essentially running from the board, across the cable, and across the board at the receiver. The optical cases are much less challenging because the transmitter is only driving to the optical module which contains its own re-timer. The same at the receiver.

The above diagram shows some of the challenges. The analog front-end (AFE) needs to handle twice the bandwidth if using PAM4, or 1.5X if using PAM6. The ADC needs reduced noise and higher accuracy. The DSP needs to handle stronger equalization, PLL needs a 50% improvement in jitter. Maximum likelihood sequence detection (MLSD) becomes more critical. All of this has to be done at a lower price and a lower energy-per-bit than 2×112G. Otherwise, why bother?

Of course, Cadence doesn't have a 224G SerDes yet, but we do have a track record in high-speed SerDes at 112G in several process nodes and meeting the most challenging extended long-reach demands. Wendy ended by inviting everyone to come and see our 112G-ELR demo at the booth...but DesignCon is over so you can't.