IEEE 1838: Taking Test into the Third Dimension

I've written quite a bit recently about advanced packaging and More than Moore technologies for building systems. For example, see my posts:

• John Park's Webinar on Chiplets
• Known Good Die
• System in Package, Why Now?
• System in Package, Why Now? Part 2
• System in Package? How to Plan and Build It

Test (or manufacturing test, to be clear what we are talking about) tends to be a second-class citizen compared to other aspects of design and manufacturing. All those sexy leading-edge processes and timing signoff in the cloud. But every design has to be tested as well as manufactured. In the 1990s, there was a time when manufacturing test looked like it was going to become more expensive than the manufacturing cost of the part. Testers, often called ATE for automated test equipment, are expensive. Tests were taking a long time. A major component of the cost of test is simply the depreciation of the tester's purchase price times the time each part takes to test.

Two things saved the situation. The first was the complete acceptance of scan-test as the way to automatically generate test programs for digital designs (or the digital part of any design—analog and memories were and are tested with different approaches). The second thing was the development of test compression and LBIST (logic build-in self-test) so that the time and memory required to run the scan-test program were significantly reduced. For more background on scan test, compression, and Cadence's solution in the space, see my posts:

• Modus Test Solution—Tests Great, Less Filling
• What Next for Modus DFT?

A New IEEE Standard

Today I'm going to look at a new standard, IEEE Std 1838-2019 which was finally published in March (yeah, so it maybe should be 2020, but it was approved by the working group in November 2019 which is apparently when the year part of the number gets locked in). This is IEEE Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits. Actually, it's even more complicated. In fact, I think you can add IEEE Standards to Bismarck's remark about nobody wanting to see how sausages or laws are created.

At the end of May, I attended a seminar presented by Erik Jan Marinissen of imec (at 5:00am California time!) on the new standard. He was Mr 1838, the founder, first chair, and is now (after reaching his end-of-term as chair) vice-chair of of the 3D Test Working Group that developed the standard and shepherded it through the IEEE. To read about my interview with Erik Jan and some of his students, see my post CDNLive: Testing Times in Munich.

3D chips have a problem with testing that a "normal" design with just a single die does not. All the pins connect to the bottom die, so test programs can only be applied to the bottom die. Somehow, the upper die need to be tested anyway, and that is what this IEEE standard addresses. Even 2.5D interposer designs don't need this (unless they also have a 3D die stack on the interposer somewhere) although they might benefit from the approach if there are individual chiplets with their own test program that can be reused.

IEEE 1149.1, 1500, and Now 1838

As Erik Jan pointed out, we seem to get a new IEEE DfT standard every 14 years. If we go back 28 years we get to IEEE 1149.1 which is more often called JTAG (for Joint Test Action Group, the people who came up with the standard).

Modular design and test allow each block in the design to be set into one of three modes via wrappers:

• BYPASS, meaning it is passing signals through but not testing anything, it is transparent
• INTEST, meaning that the internals of the module are being tested
• EXTEST, meaning that the connections between the module and the rest of the design (in particular, for this standard, the die above and below, along with any "shore" logic) are being tested.

For example, to test module B in the diagram above, set the modules on the left and right to BYPASS, and the module in the middle to INTEST.

JTAG is mostly focused on EXTEST, for testing the connectivity in the packages and circuit boards. This allows an assembled board to be tested simply. Even if you have an expensive bed-of-nail tester, modern multi-layer circuit boards just don't have enough access. It is the most successful test standard in the world. It can also be used to get test signals into the chip, and in fact, a lot of embedded software debug makes use of JTAG to get to do things like set breakpoints.

Fourteen years ago (and fourteen years after JTAG) was IEEE 1500 focused on INTEST of SoCs with lots of cores, and EXTEST of how the cores were assembled.

For the new standard, the elements are 3D stacked die. This table shows how the three standards are both the same and different:

The heart of the new standard are “test elevators” (a term coined by Erik Jan) to get test data from the external interface (usually the bottom side of the bottom die—but it also works with a wirebonded design accessed through the top die). Each die (possibly excluding the last one) has an interface to bring signals up from the die below, and an interface to pass signals up to the die above. It can also take the test data coming up and use it for testing that individual die. There is also a loopback in the standard, so that a partial stack missing its top die can also be tested.

I think that there are several major benefits to the standard. The first is that companies that produce EDA software that creates test programs (such as Cadence's Modus) can focus on the standard and know that it should work with all die stacks. Obviously, people creating 3D designs can take advantage of the standard, too.

Today, many system-in-package designs are created by one company—all the die are designed to work together from the start. But that is not expected to always be the case, and the standard should work with "standard" chiplets that were not explicitly designed to work together. This is the second major aspect of the standard: die that were not designed to work together can be stacked and tested.

But there is a major caveat here. The 1838 standard only covers test. In particular, it doesn't address how to align the mechanical and electrical aspects of the die stacking (such as microbumps and TSVs), nor thermal and other issues important in system-in-package designs.

The new standard inherits many aspects of the serial control mechanism first built into JTAG (1149.1) via the Test Access Port (TAP). This is five pins (reset is optional in 1149.1 but not 1838) and the TAP controller on the module. PTAP is the primary test access port. STAP is the secondary test access port (the same but mirrored interface). The STAP communicates with the next PTAP. There may be multiple STAPs (STAP1, STAP2, etc) if there are multiple stacks on top, as in the diagram:

The standard specifies three aspects (one of which is optional):

1. DWR, the Die Wrapper Register, based on IEEE 1500
2. SCM, the Serial Control Mechanism, based on IEEE 1149.1
3. FPP, a Flexible Parallel Port (so flexible it is optional). This can be used to reduce test time. Erik Jan describes this as "freeway versus country road"

The diagram shows how the various aspects fit together in a die stack. Note that the top die can be created with no mechanism for another die to go on top (for example, if it is a CMOS image sensor), or it can have unused interfaces on top but can still be fully tested. There are two interfaces on each die, known as the primary and secondary. The secondary interface of one die plugs into the primary interface of the next die. They may be on different sides of the die (as in the diagram) or all on one side (for interposer type designs, maybe). But the standard doesn't insist on one way or the other.

There's a lot more detail in the standard. You work in the area, I'm not going to pretend that this blog is any substitute for the standard itself. My aim is more to give people who are not specialists an idea of what the standard contains, in a similar way to how even embedded software engineers need some limited knowledge of JTAG.

Cadence and 1838

Cadence was quoted about the new standard in imec's press release. Wolfgang Meyer said:

A DfT standard like IEEE Std 1838 is important to the industry. Die makers know what they must provide, and stack integrators know what they can expect. Moreover, EDA suppliers like Cadence can focus their tool support on architectures that are compliant with the new standard. It is good that there is some user-defined scalability with the standard as the 3D-IC field is so wide—a rigid ‘one-size-fits-all’ standard would not work.

I asked Erik Jan after the webinar about where Cadence's implementation is, since he has been working with us (along with a series of students who worked as Cadence residents with him at imec):

Regarding Cadence tooling for IEEE Std 1838: as you might recall, my first Joint Development contract with Cadence was on 3D-DfT. In the period 2010-2015, I collaborated together with the Cadence DfT development team in Endicott, NY on automating the 3D-DfT insertion and subsequent expansion from tests defined at die level into tests for that die but defined at the stack level.

At the time, our entire 3D-DfT solution was based on IEEE Std 1500, i.e., the wrapper standard for embedded cores in SoCs. As Cadence has tooling for hierarchical test of core-based SoCs, we could reuse that, with some adaptations, for 3D die stacks too. Different customers have different ideas ablut their (2D) DfT architectures, and hence DfT insertion tools typically perform a number of basic DfT insertion operations, which users end up using as building block in a Tcl script that does the DfT insertion in the way they like it (which is different in different companies; even sometimes within a single company!). So, all we needed to do is adapt the Tcl scripts to also automate the 3D-DfT insertion (on top of the 2D-DfT insertion).

Learn More

Here's the summary of the standard:

IEEE Std 1838 is a die-centric standard; it applies to a die that is intended to be part of a multi-die stack. This standard defines die-level features that, when compliant dies are brought together in a stack, comprise a stack-level architecture that enables transportation of control and data signals for the test of (1) intra-die circuitry and (2) inter-die interconnects in both (a) pre-stacking and (b) post-stacking situations, the latter for both partial and complete stacks in both pre-packaging, post-packaging, and board-level situations. The primary focus of inter-die interconnect technology addressed by this standard is through-silicon vias (TSVs); however, this does not preclude its use with other interconnect technologies such as wire-bonding.

You can purchase the standard from the IEEE website (or, if your organization has the right subscription, just download it).

You might also consider Handbook of 3D Integration, Volume 4: Design, Test, and Thermal Management of which Erik Jan is one of the editors. Volumes 1-3 cover other aspects than test (which are also important! Just not today's topic). It will cost you around $150 (but it is nearly 500 pages long).

 

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