Machine Learning in EDA: Videos and More

At a recent keynote, Bill Dally, the chief scientist at NVIDIA, said that the company is using AI to design better chips. He continued:

AI will have a profound impact on the process of chip design.

Here at Cadence, we couldn't agree more. In fact, over the last couple of years we have added aspects of deep learning to many of our tools. I have written a fair bit about this, both the general topic and also the capabilities of machine learning added to various tools.

My most recent general post was Machine Learning in EDA.

Some of the posts covering specific tools were:

• Machine Learning in JasperGold
• Xcelium ML: Black-Belt Verification Engineer in a Tool
• Under the Hood of Xcelium ML
• Allegro X, the Design Platform for the Next Generation of Intelligent System Design
• Liberate Trio: Characterization Suite in the Cloud
• Cerebrus: The Future of Intelligent Chip Design

Breakfast Bytes is not the only place where coverage of Cadence's machine learning (often called AI, but at least here I use the terms interchangeable). I'm going to link to several other resources. I'm sticking to the ones that are public, there are more videos and documents behind the registration wall, but there is enough stuff outside than anyone can access.

Here's an article that you might have missed: Cadence's CEO (now, but not when this article was published) Anirudh Devgan in EE Times, Cracking Intractable Chip Design Challenges with the Help of Machine Learning.

If you prefer to consume your information in video, here's a presentation from the recent DAC AI Revolutionizing EDA:

Implementation

Focusing down on implementation, let's start with a white paper Machine Learning-Driven Full-Flow Chip Design Automation.

Here's another video Cerebrus Intelligent Chip Explorer Automated ML Chip Design Technology Overview:

And now for some videos from our customers. First, Samsung with Cerebrus ML Flow Optimization Delivers Better PPA for Latest Samsung Advanced Nodes:

And Renesas with Renesas Adopts Cadence Cerebrus Intelligent Chip Explorer for AI-Driven Digital Flow Optimization:

Tensilica

Let's wrap up with a presentation about Tensilica from a Linley Processor Conference Cadence: Efficient Machine Learning on DSPs Using TensorFlow:

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