Today it is TSMC's Open Innovation Platform Ecosystem Forum, or OIP for short. This is one of two events each year at which TSMC presents much of the status of their technology, their fab construction, and production schedules. The other is the TSMC Technology Symposium, normally held in early May. I covered this year's Technology Symposium in three posts:

• TSMC Technology Roadmap
• TSMC: Specialty Technologies
• TSMC: Zero Excursion, Zero Defect

I wrote about last year's TSMC OIP in:

• TSMC OIP Virtual Design Environment
• TSMC OIP Ecosystem Forum

New Process Certifications

At TSMC OIP today, Cadence announced the certification of the Cadence EDA tool portfolio on TSMCs N6 and N5P processes. We also announced that we are working on customers on N6 design starts for both production designs and test chips, and have an active N5P customer engagement underway. This certification covers both the Cadence digital and signoff tools, as well as the custom/analog tools. I'm not going to list them all here. There is more detail in the press release. Note that Cadence previously announced the certification of digital and analog tool flows for N5 (at last year's OIP). The one-sentence summary is that all Cadence tools are supported on all available TSMC processes.

The secret decoder ring for TSMC's current processes:

• N7 is the 7nm process in full volume production without EUV.
• N7+ is the second-generation 7nm process using some EUV layers, also in full volume production.
• N6 is a shrink of N7+ giving more performance and an 18% logic density gain.
• N5 is the 5nm process currently in risk production.
• N5P is the performance-enhanced 5nm process.

For the most up-to-date details on TSMC's processes, see the first post that I linked to above TSMC Technology Roadmap. I will be attending OIP today and I expect that there will be a limited update on the status and timetables of TSMC's processes. Watch for a post, probably next week.

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