Never miss a story from Breakfast Bytes. Subscribe for in-depth analysis and articles.
At the recent 2021 TSMC OIP Ecosystem Forum, there were two special presentations by TSMC "before" the usual partner presentations. I put "before" in quotes since the event was virtual, so in practice, you could watch stuff in any order, unlike when OIP has been in-person in the past. I covered the first in TSMC OIP 2021: N3 HPC. The second of these was on 3D packaging, which is today's post.
It was presented by Jim Chang, Department Manager of 3dIC Design Methodology. His presentation was titled 3DIC Design Challenges and Solutions.
Jim started by running through the current offerings that make up 3DFabric. The above chart is a summary, but I've written often enough about TSMC's CoWoS and InFO. I'm just going to assume that you know what these capabilities provide. I'm also not going to try and convince you that 3DIC, in general, is increasing in importance. I've done plenty of posts on this too. I'm just going to take it as given that More than Moore is a thing now.
TSMC successfully taped out its first TSMC SoIC eTV testchip earlier this year. It was a face-to-back design with 9um TSV pitch. The top die is an N5 Arm CPU chip. The bottom die is 40MB N6 SRAM chip. There is a high-speed chip-to-chip I/O interface.
There a several steps to the successful design of a multi-die design like this, as you can see in the diagram above.
The first step is system partitioning. First the design is partitioned to maximize system performance, and this dictates the number of signals between the chips. Then choice of chip-to-chip interface needs to be decided to balance bandwidth, latency, and the number of signals. Then detailed planning of the placement of TSVs (or bonds) must be planned to meet both bandwidth requirements and signal integrity requirements.
There are always thermal challenges in 3DICs of all types, since heat escaping one die often has to do so by passing through another, so the thermal pattern on a die in a 3DIC can be quite different from if it was packaged individually. Conventional thermal analysis uses a coarse grid to improve runtime, but unique chimney structures can exist in 3DIC since metal is not just an electrical conductor but a thermal conductor. The conductivity of the metal is about 1600X that of the dielectric, so pretty much all the heat follows the metal paths. Also, every IC has a power-delivery-network that connects all the way from the transistors to the bumps at the top. So the PDN behaves like a chimney, taking all the heat out through the roof.
Using a coarse grid rather than a golden approach results in errors in the temperature of up to 10%, which is significant, but it is too expensive computationally to maintain maximum accuracy everywhere. Instead, a multi-step approach is used, where the coarse-grained approach is used to identify hot spots, and then fine-grained detailed analysis is used. This hierarchical approach makes it possible to detect the temperature of the hotspots with high accuracy without an excessive runtime.
For the chip-to-chip interface, TSMC offers Lite-IO interface IP. This improves bitrate from 2Gbps to 4Gbps, reduces channel capacitance through driver/ESD/antenna layout and design rule co-optimization, and reduces 6σ clock skew by over 100ps with a customized clock tree.
Next, Jim covered testing 3D stacks. I've covered that earlier in IEEE 1838: Taking Test into the Third Dimension and this is the approach that TSMC uses.
Historically, InFO designs have largely been done manually, but that is not practical for this style of design due to the number of connections. TSMC created an InFO technology file in the tradition of place and route so that the design can be handled automatically from constraints, to routing, to DRC fixing, and final DRC check. Obviously, this is a huge productivity boost.
Next, timing signoff. The corner combination grows as the products of the corners from each chip. Efficient hierarchical STA needs to focus on interface chips. I've covered that in my posts:
Finally, multi-chip physical verification. The key is to find the right balance between IR-drop and TSV usage. A complication is that the power grid is constrained from both sides with bond landing on one side and TSVs on the other, with the potential for current hotspots if not enough care is taken. Another issue is that TSVs have relatively large keep-out-zones (KOZ) where active circuitry cannot go (due to stress during TSV manufacture).
Jim's Conclusion: The Future of 3DIC Has Arrived! And here is the readiness of the Cadence tools.
Sign up for Sunday Brunch, the weekly Breakfast Bytes email.