There are lots of books on EDA, but many of them are academic texts about the algorithms used inside EDA tools. Rather fewer of them are written for people doing real designs. A recently published book firmly targeted at the practical needs of real design teams is VLSI Design Methodology Development. It is written by Tom Dillinger, who was another member of the writing team at SemiWiki when I was there. When I first met him, he was working at Oracle on server chip design. He had been doing that at Sun when Oracle acquired them. The chip he was working on didn't change, just the name on the front of the building. He also worked at AMD and IBM.

The book is available on Amazon. I'm afraid it is nearly $90 like most books with, let's face it, a somewhat limited audience. It is also available from the publisher Pearson (Prentice-Hall) for the full list price of $120. But you get a lot of book for your money: the book is just over 750 pages long.

It is intended to be a textbook, as well as of interest to working design teams. As it says in the preface:

The audience for the text is senior-level undergraduates and first-year graduate students studying microelectronics. Profession engineers will also likely find topics of interest to expand the breadth of their expertise. In many cases, the discussion of a specific step extends beyond the design engineering considerations to include the perspective of a project manager, a design automation engineer, a fabrication technology support engineer, and, to be sure, a member of the project methodology team.

The book opens with an anonymous quote, that could serve as the leitmotiv that runs through the whole book:

There is no single right way to design a chip, but there sure are many wrong ways.

The book explains the pros and cons of various approaches to putting together a design flow. It doesn't assume a lot of knowledge. For example, it doesn't really assume you know what a standard cell is, or a timing constraint. The end result is that the book goes over a lot of the right ways to put together a design methodology while guiding you away from the wrong ways.

I'm not going to pretend that I've read all 750 pages of the book, but I have dipped into it. The book goes up to the present, in the sense that it covers multi-patterning and EUV extensively, advantages and challenges of designing with FinFETs, FD-SOI, multiple clock domains, dynamic voltage, and frequency scaling (DVFS), and so on. It also includes a wealth of advice that stems from Tom's many years of experience in designing some of the most advanced microprocessors of the era.

I think that most people will learn something from this book. Inevitably, we all end up being somewhat specialized and have very in-depth knowledge about one area in particular, such as logic synthesis, formal verification, or IR drop analysis. This book fills in a lot of color to give a deeper understanding of the rest of the design flow.

Here are the contents, to give you a good idea of the scope of the book.

Contents at a Glance

The book is broken up into six topics, with a few chapters in each. Each chapter is further subdivided, but let me just give you the topic and chapter structure, which gives you a good idea of the breadth that the book covers.

• Preface
• Topic I: Overview of Design Methodology
  • Chapter 1: Introduction
  • Chapter 2: VLSI Design Methodology
  • Chapter 3: Hierarchical Design Decomposition
• Topic II: Modeling
  • Chapter 4: Cell and IP Modeling
• Topic III: Design Validation
  • Chapter 5: Characteristics of Functional Validation
  • Chapter 6: Characteristics of Formal Equivalency Validation
• Topic IV: Design Implementation
  • Chapter 7: Logic Synthesis
  • Chapter 8: Placement
  • Chapter 9: Routing
• Topic V: Electrical Analysis
  • Chapter 10: Layout Parasitic Extraction and Electrical Modeling
  • Chapter 11: Timing Analysis
  • Chapter 12: Noise Analysis
  • Chapter 13: Power Analysis
  • Chapter 14: Power Rail Voltage Drop Analysis
  • Chapter 15: Electromigration (EM) Reliability Analysis
  • Chapter 16: Miscellaneous Electrical Analysis Requirements
• Topic VI: Preparation for Manufacturing Release and Bring-Up
  • Chapter 17: ECOs
  • Chapter 18: Physical Design Verification
  • Chapter 19: Design for Testability Analysis
  • Chapter 20: Preparation for Tapeout
  • Chapter 21: Post-Silicon Debug and Characterization ("Bring-Up") and Product Qualification
• Epilogue

The Future

The book doesn't cover absolutely everything. As Tom says in the Epilogue, there are emerging technologies that are beyond the scope of the book but which may quickly become required expertise for microelectronic engineers. In fact, most of these trends are things I've written about too. Here is Tom's list, each with a link to my latest take on the topic.

• Advanced packaging technologies, often called More than Moore: To get an idea of just how quickly this is happening, see my post from HOT CHIPS just a couple of months ago: HOT CHIPS: Chipletifying Designs.
• Analog/mixed-signal IP modeling: Tom includes things like SerDes modeling and IBIS-AMI models. See my posts AMI and IBIS: Who Put the Eye in AMI? and AMI for DDR5 Made Easy.
• Emerging memory IP technologies: For more on that, see my post Emerging Memories Poised to Explode.
• New device materials for interconnects and dielectrics: For more on that topic, see my post IEDM: The World After Copper.
• Integrated Si photonics structures: For an introduction see my post Silicon Photonics from a couple of years ago or more recently start with Diwali, the Hindu Festival of Lights...and Photonics, the Silicon Festival of Light.
• New behavioral modeling languages and synthesis support: For a design done starting with MATLAB, see Designing a Wi-Fi HaLow Baseband in Less than Six Months. For a design done starting with TensorFlow, see Building Neural Networks with High-Level Synthesis.

Further Information

Buy the book and read it!

The book does have its own website, with additional technical references, errata, and more.

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