TSMC OIP: 3DFabric and Integrity 3D-IC

Today is TSMC's OIP (or, to give it its full name, TSMC 2021 Online OIP Ecosystem Forum). I will be attending and so you can expect a few blog posts covering the material presented in the coming week or two.

In the meantime, Cadence made three TSMC-related announcements. Two I wrote about last week in TSMC OIP: N3, N4, and PCIe 6.0. Today, it is the third.

Integrity Enabled for 3DFabric

Recently, Cadence announced the Integrity 3D-IC Plattform. See my post Introducing the Integrity 3D-IC Platform for Multi-Chiplet Design for details. At OIP last year, TSMC announced that all their 3D packaging technologies were being grouped under the name 3DFabric. See my post TSMC: Specialty Processes and Specialty Packaging for my coverage of that.

I can't do much better to cover this announcement than lightly edit the first paragraph of the press release:

Cadence today announced that it is working with TSMC to accelerate 3D-IC multi-chiplet design innovation. As part of the collaboration, the Cadence Integrity 3D-IC platform, the industry’s first unified platform for 3D-IC planning, implementation and system analysis, is enabled for TSMC’s family of 3DFabric technologies. In addition, Cadence and TSMC co-developed a methodology to dramatically reduce the number of signoff corners and speed time to tapeout via the Cadence Tempus Timing Signoff Solution. Through these latest milestones, customers can confidently adopt the Cadence 3D-IC solution and TSMC’s 3DFabric technologies to create competitive hyperscale computing, mobile and automotive applications. The Cadence 3D-IC solution supports TSMC’s full set of 3D silicon stacking and advanced packaging technologies, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS) and System-on-Integrated-Chips (SoIC).

In more detail:

• The Cadence 3D-IC solution centers on the Integrity 3D-IC platform, which provides integrated planning, implementation and system analysis to optimize PPA for multi-chiplet systems
• The Tempus Timing Signoff Solution with rapid automated inter-die analysis and STA technologies results in faster time to tapeout
• The Voltus IC Power Integrity Solution, tightly coupled with the Celsius Thermal Solver, facilitates early multi-die IR drop and thermal analysis for design robustness
• Customers can confidently adopt the Cadence 3D-IC solution and TSMC’s family of 3DFabric technologies to create next-generation hyperscale computing, mobile, and automotive applications

Why 3D-IC?

Various forms of 3D-IC have been around for a long time. Multi-chip modules have been used for RF for decades. CMOS Image Sensors (CIS) have had the sensor and the logic to process the pixels sandwiched together for years. Various forms of putting memory in the same package as a processor have been used. HBM is up to HBM3 now, and the original HBM was standardized by JEDEC in 2013. So what has caused the recent huge increase in the various forms of 3D-IC.

I think that at one level it is that 3D-IC has gone from a niche to high-volume, and as always with high volume comes lower cost. This has changed the attractiveness of doing all the integration on a single SoC versus doing some of the integration using multiple chiplets (die) in a more complex package. Here are several reasons that Moore than More is suddenly more attractive than just Moore:

• Some designs are too big for a single reticle, so you have no choice but to go for multiple die
• Some things (analog, RF) are difficult to do and get no advantage from the most advanced nodes
• IP availability (e.g., SerDes or DDR or PCIe) may not yet be available in the most advanced node...but they are available in the prior node
• It makes no sense to design an entire system in an advanced node when only some parts of the system require it or can take advantage of it. 3D-IC can be cheaper than doing a big monolithic integration
• Two (or more) small die yield better than the same silicon on a single die
• You can't get enough memory on the monolithic die (or you want memory like DRAM that requires a different process)
• If you use the prior generation for I/O devices (such as SerDes) then the current generation test chips are not on your critical path

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