Digital Design: The Year That Was — New Training Releases, Blogs, and Digital Badges in 2022

Another year has gone by, and we have evolved back into the new and old “normals,” partially moving back to the office and Live Trainings using the hybrid working to improve efficiency and sustainability for our customers as best as possible.

We thought it would be a good idea to take a look back at our blogs and other exciting news around Digital Design and Signoff in 2022.

Most Viewed Blogs

The following are the most viewed blogs in 2022:

• RTL-to-GDSII Flow: I Am Not a Tool But Can Help You Implement Your Entire Design! By P Saisrinivas
• Floorplanning Frustrations Got You Down? Help Is on the Way! By Vinita Nelson
• Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI? By Neha Joshi

Other News from 2022

We conducted many webinars throughout the year. If you have missed any of these, you can find recordings on the Webinars page. These can also be accessed by searching Cadence Learning and Support Portal with the “webinar” keyword.

Most Viewed RAKs

Following are the most viewed RAKs in 2022:

• Tempus ECO RAK by Ayush Srivastava and Marc Heyberger
• Stylus Flowkit RAK by Benoit Carpentier and Jason Dlugosch
• Genus/Modus: PMBIST Deep Dive RAK by Patrick, Joyce Kraley, and Ke Zhang

New Training Released in 2022

• Cadence Cerebrus Intelligent Chip Explorer Training; also available online.

The Cadence® Cerebrus Intelligent Chip Explorer is a revolutionary and machine-learning-driven automated approach to chip design flow optimization. Block engineers specify design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet these power, performance, and area (PPA) goals in a completely automated way. By adopting Cadence Cerebrus, engineers can concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s evermore powerful electronic systems.

You can find related training bytes on Cadence Learning and Support Portal and search with “Cerebrus” as a keyword.

Here’s a blog with an interesting case study:

What's Behind the 5% Die-Area Shrink and 12% Power Saving by MediaTek?

• Genus Low-Power Synthesis Flow with IEEE 1801 Training; also available online and with Badge Exam.

You can also get further information in this blog.

Newly Created

Digital Badges

Newly Released Training Versions

Voltus Power Grid Analysis and Signoff with Stylus Common UI v22.1 (online)

Tempus Signoff Timing Analysis and Closure with Stylus Common UI v22.1 (online)

Innovus Block Implementation with Stylus Common UI v22.1 (online)

The Training Bytes blog series helped promote some of our training bytes, webinars, and scheduled dates for our "Blended" and "Live" trainings. The series also popularized our digital badges. For further information about our trainings, see the Training page and get a complete training overview in our learning map.

We hope that our blog series helped you address your tasks faster and with ease. If you have any suggestions or desired topics on which you want us to blog, do let us know! You can also reach out to us at Cadence Training for information on courses, schedules, online trainings, or live on-site trainings.