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Featured

When AI Becomes Part of Your Analog Design Workflow

If you design analog or mixed-signal circuits, each silicon generation asks you to…

Corporate
• 6 min read
Virtuoso AI Studio , featured , agentic ai , IP Catalog , analog design

Virtuoso Studio IC25.1 ISR8 Now Available

Virtuoso Studio IC25.1 ISR8 production release is now available for download.

Virtuoso Release Team
• 5 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Analog Design Migration Made Easy With Migration Cockpit

Analog IP remains one of the most valuable and difficult-to-scale assets in semiconductor…

Vinod Khera
• 5 min read
featured , analog IP , Automated test bench migration , parasitic aware optimization , Front to back Analog Migration
Analog/Custom Design
Latest blogs

Virtuosity: 10 Things I Learned In January By Browsing Cadence Online Support

This month's highlighted content includes helpful information on wreal modeling,…

• 2 min read
Virtuoso Space-based Router , Rapid Adoption Kit , encounter , calibration , Virtuoso , Analog Design Environment , ADE-XL , AMS simulation , mixed signal , interoperability , wreal , Custom IC Design

Things You Didn't Know About Virtuoso: Drag and Drop

I love it when I'm sitting in a meeting with my colleagues or with a group of customers…

• 2 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , IC 6.1 , VIrtuoso drag and drop , IC 6.1.5 , ADE , Virtuoso , ViVA , ADE-XL , drag and drop , Custom IC Design

Introduction to Cadence Virtuoso Advanced Node Design Environment

What can designers do about advanced node technology? This is an introduction to…

• 6 min read
STI , Virtuoso Advanced Node , length of diffusion , custom/analog , Routing , analog prototyping , Double Patterning , layout-dependent effects , Ishikawa , custom , odd-loop marker , 20nm , Advanced Node , module generation , analog , WPE , design flow , LDE , dynamic coloring , LOD , well proximity , Placement , stress , interconnect layers , Custom IC Design , local interconnect

Virtuosity: 10 Things I Learned in December By Browsing Cadence Online Support

In addition to the R&D engineers who actually develop our software, the folks in…

• 4 min read
Variability Aware Design , AMS , Analog Design Environment , Virtuoso IC6.1.5 , Virtuoso Space-based Router , VSR , Analog Simulation , Cadence Space-based Router , workshop , IC615 , IC 6.1.5 , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , Schematic Editor , ViVA , ADE-XL , mixed signal , Custom IC Design , Virtuoso Layout Suite

Library "Safe Margins" -- Are They Really Saving Your Design?

Designers need to radically re-think their strategies for timing closure to get the…

• 4 min read
Standard Cell , memory characterization , Process Variation , Elzeftaki , library characterization , Timing Closure , Complex IO , PVT corners , safe margins , Complex Cell

SKILL for the Skilled: Part 6, Many Ways to Sum a List

In a previous post I presented sumlist_2b as a function that would sum lists of length…

• 5 min read
Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitmen…

Cadence holds a leading position in the EDA industry due to its broad product portfolio…

• 1 min read
CDNLive , cadence , AMS Designer , custom , Design Challenges , analog , web page , Mixed-Signal Methodology Guide , Mixed-Signal , Mixed-signal solutions web page , Virtuoso , mixed-signal book , digital , implementation , mixed signal , Encounter Digital Platform , web site , verification

Mixed Signal Technology Summit Proceedings Now Available

In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California…

• 5 min read
Static timing analysis , mixed-signal seminars , AMS , static analysis , EDI , microcontrollers , ARM Cortex M0 , mixed signal design , cadence , Functional Verification , mixed signal methodology , mixed signal solution , Open Access , STA , Verilog-AMS , timing model , FTM , Mixed-Signal , MCUs , encounter , Mixed-Signal Technology Summit , analog behavoral , analog behavioral models , analog/mixed-signal , mixed signal physical implementation open access , model validation , Signal Integrity , Virtuoso , Spectre , Cortex-M0 , oa , RNM , mixed signal methodology guide , real number types , Mixed signal physical implementation , behavioral models , mixed signal , OA: OpenAccess , cortex M , mixed-signal design , wreal , real number models , ARM , ARM-Cortex-M , OpenAccess , SPICE , mixed signal implementation , liberty model , simulation , AMS Verification

Mixed-Signal Technology Summit in Japan Provides Technology Updates

Japan’s semiconductor industry is undergoing a significant change in recent years…

• 3 min read
AMS , uvm , Virtuoso-AMS , microcontrollers , ARM Cortex M0 , mixed signal design , Mixed-Signal On Top , AMS-Designer , MS ToT , IC 6.1 , A/MS , mixed signal methodology , tech on tour , AMS Designer , analog on top , Open Access , Cortex-M , Verilog-AMS , analog , Mixed-Signal , encounter , Mixed-Signal Technology Summit , LDE , analog behavioral models , analog/mixed-signal , Virtuoso , mixed-signal book , Cortex-M0 , oa , ClioSoft , metric-driven verification , mixed signal , wreal , micro-controllers , ARM , ARM-Cortex-M , OpenAccess , Common Power Format , AMS Verification , TowerJazz , Matlab , real number

SKILL for the Skilled: Part 5, Many Ways to Sum a List

In the most recent posts of SKILL for the Skilled (see previous post here ) we looked…

• 5 min read
Team SKILL , Jim Newton , summing , Virtuoso , Lisp , SKILL++ , sumlist , SKILL

Discussing Mixed Signal -- New On-Line Forum, and 3-Day Training Classes

Are you working in the area of mixed signal? Then you may want to exchange information…

• 1 min read
ITDB , mixed-signal training , Andreas Lenz , analog on top , CPF , Mixed-Signal , encounter , Virtuoso , mixed signal , mixed-signal forum , OpenAccess , forum , Cadence Community

Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical…

The recently concluded ARM TechCon 2012 , the annual event for ARM users (including…

• 2 min read
ARM Techcon , EDI , chipestimate , ARM Cortex M0 , AMS Designer , ARM Technology Symposium , 20nm , 14nm , Mixed-Signal , Virtuoso , mixed-signal book , Cortex-M0 , mixed signal , mixed-signal design , ARM , ARM-Cortex-M

Recent Events Show That Customer Interest in Mixed-Signal Remains High

The well attended Mixed-Signal Technology Summit last month really demonstrated the…

• 2 min read
ARM Techcon , ARM Cortex M0 , mixed signal design , Technology on tour , MS ToT , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , Open Access , Cortex-M , Mixed-Signal , Mixed-Signal Technology Summit , analog/mixed-signal , mixed-signal book , Cortex-M0 , Mixed-Signal Tech Summit , mixed signal methodology guide , mixed signal , OA: OpenAccess , cortex M , mixed-signal design , ARM , Mixed-Signal Methodology Book , tech-on-tour , OpenAccess , AMS Verification

Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and…

A press release and a blog post caught my attention this week (October 15, 2012)…

• 2 min read
AMS , EDI , ets , uvm , microcontrollers , ARM Cortex M0 , Mixed-Signal On Top , MS ToT , cadence , AMS Designer , TSMC , EPS , Mixed-Signal , Virtuoso , mixed signal methodology guide , mixed signal , PVS , ARM , encounter power system , Encounter Timing System , IUS

SKILL for the Skilled: Part 4, Many Ways to Sum a List

In the previous posts SKILL for the Skilled: Many Ways to Sum a List (Parts 1, 2…

• 5 min read
Team SKILL , Virtuoso IC6.1.5 , Jim Newton , sum a list , SKILL for the Skilled , recursion , Virtuoso , Lisp , SKILL++

ARM-Based Microcontrollers using Cadence’s Mixed-Signal Solution

I recently came across a Wall Street Journal article, "ARM Chases Bigger Slice of…

• 2 min read
DAC , microcontrollers , Demo , Cortex-M , MCUs , Virtuoso , Cortex-M0 , incyte , fuel injection system , System Design Kit , micro-controllers , ARM , Balasubramanian

SKILL for the Skilled: Part 3, Many Ways to Sum a List

In Part 1 and Part 2 of this series of posts, I showed a couple of ways to sum up…

• 4 min read
recursive functions , Team SKILL , Jim Newton , sum a list , SKILL for the Skilled , recursion , Virtuoso , Lisp , Custom IC Design , SKILL++

SKILL for the Skilled: Part 2, Many Ways to Sum a List

In the previous posting, SKILL for the Skilled: Many Ways to Sum a List (Part 1 …

• 4 min read
Team SKILL , Jim Newton , sum a list , summing , Virtuoso , software development , SKILL++ , SKILL

Things You Didn't Know About Virtuoso: The (Setup) State of Things

Apologies for the long delay between articles (best intentions and all that). I last…

• 3 min read
Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , setup states , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Custom IC Design

SKILL for the Skilled: Part 1, Many Ways to Sum a List

A while back I presented a one day SKILL++ seminar to a group of beginner and advanced…

• 3 min read
Jim Newton , sum a list , summing , Virtuoso , apply , software development , SKILL++ , sumlist , SKILL

Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Even though it's been over 2 months since this year's Design Automation Conference…

• 3 min read
real number modeling , DAC , uvm , IP , A/MS , Verilog-AMS , analog , co-simulation , Mixed-Signal , analog behavioral models , analog/mixed-signal , model validation , RNM , metric-driven verification , VHDL-AMS , assertions , mixed signal , mixed-signal design , wreal , real number models , Design Automation Conference , SPICE , mixed-signal verification , verification , stmicroelectronics , real number

Mixed-Signal Gets Clear Message in China

While most of my colleagues in the US were taking a nice break during the July 4…

• 3 min read
mixed-signal seminars , Beijing , AMS , China , mixed signal design , Technology on tour , mixed-signal ToT , mixed-signal methodology , mixed signal methodology , tech on tour , mixed signal solution , analog , Mixed-Signal , Shenzhen , mixed signal methodology guide , mixed signal , ARM , tech-on-tour , Shanghai , AMS Verification , mixed-signal verification

Tech-On-Tour: Bringing Advanced Mixed-Signal Design Methodology from Concepts to…

About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed…

• 1 min read
DAC , Technology on tour , mixed-signal methodology , tech on tour , CPF , Mixed-Signal , encounter , Virtuoso , Cortex-M0 , incyte , mixed signal , Mixed-Signal Methodology Book , tech-on-tour , OpenAccess

What’s Hot for Mixed-Signal At DAC?

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At…

• 2 min read
DAC , AMS , mixed signal design , mixed-signal methodology , mixed signal methodology , mixed signal solution , 28nm , 20nm , Advanced Node , Mixed-Signal , mixed signal physical implementation open access , mixed-signal book , mixed signal methodology guide , low-power design , mixed signal , cortex M , mixed-signal design , power , Design Automation Conference , mixed signal implementation , digitally assisted analog , mixed-signal verification

Cadence To Release the Industry's First Mixed-Signal Methodology Book

The new era of “Internet Everywhere” creates a whole new spectrum of applications…

• 1 min read
AMS , mixed signal design , mixed-signal methodology , mixed signal methodology , mixed signal solution , analog , Mixed-Signal , mixed-signal book , dac2012 , mixed signal methodology guide , Mixed signal physical implementation , DAC 2012 , mixed-signal design , mixed signal implementation , mixed-signal verification

Managing Inherited Connections with CPF in Virtuoso

Let's assume you are managing a schematic-driven top level design in Virtuoso and…

• 4 min read
inherited connections , EDI , Low Power , mixed signal solution , CPF , analog , Mixed-Signal , encounter , Verilog , mixed signal physical implementation open access , Virtuoso , oa , Mixed signal physical implementation , mixed signal , OA: OpenAccess , mixed-signal design , Virtuoso environment , mixed signal implementation , design implementation , Common Power Format

Things You Didn't Know About Virtuoso: Rapid Adoption Kits

This post isn't directly about tips and tricks for getting the most out of Virtuoso…

• 1 min read
Virtuoso IC6.1.5 , Rapid Adoption Kit , workshop , analog , Constraint-driven , Virtuoso , ViVA , Connectivity-driven , Custom IC Design , RAKs , Virtuoso Layout Suite XL

A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

The purpose for creating a Pcell is to automate the creation of data. Pcells should…

• 3 min read
ECO , Static timing analysis , EDI , mixed signal design , parasitic , IC 6.1 , mixed signal solution , Open Access , STA , timing model , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , EDIS , ECOs and PCells , Mixed signal physical implementation , mixed signal , signoff , OpenAccess , Virtuoso environment , mixed signal implementation
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