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Featured

When AI Becomes Part of Your Analog Design Workflow

If you design analog or mixed-signal circuits, each silicon generation asks you to…

Corporate
• 6 min read
Virtuoso AI Studio , featured , agentic ai , IP Catalog , analog design

Virtuoso Studio IC25.1 ISR8 Now Available

Virtuoso Studio IC25.1 ISR8 production release is now available for download.

Virtuoso Release Team
• 5 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Analog Design Migration Made Easy With Migration Cockpit

Analog IP remains one of the most valuable and difficult-to-scale assets in semiconductor…

Vinod Khera
• 5 min read
featured , analog IP , Automated test bench migration , parasitic aware optimization , Front to back Analog Migration
Analog/Custom Design
Latest blogs

SKILL for the Skilled: Virtuoso Applications of SKILL++

In this posting, I continue looking at applications of SKILL++. In particular, I…

• 4 min read
Team SKILL , Virtuoso IC6.1.5 , closures , IC 6.1.5 , sort , Virtuoso , Lisp , Custom IC Design , SKILL++ , sorting , SKILL

CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)

We have been talking about low power simulation and the Common Power Format (CPF…

• 2 min read
Low Power , CPF , Verilog-AMS , analog , Mixed-Signal , Spectre , Connect Module , mixed signal , wreal , SPICE

Virtuoso Analog Design Environment XL – Embrace the Productivity

In my last blog, Virtuoso IC 5.1.41 was Good but Virtuoso IC6.1 is Better , I wrote…

• 4 min read
parasitic-aware design , Analog Design Environment , PAD , Virtuoso IC6.1.5 , Analog Simulation , analog , IC 6.1.5 , ADE , ADEnalog , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Parasitic analysis , Custom IC Design

SKILL for the Skilled: Sorting With SKILL++

In the previous couple of SKILL for the Skilled postings we looked at some of the…

• 6 min read
Team SKILL , programming , functions , sort , Virtuoso , SKILL++ , sorting , SKILL

Thing You Didn't Know About Virtuoso: Redux

After a long break, I'm going to try to venture back into the blogosphere, starting…

• 1 min read
Virtuoso IC6.1.5 , Search Assistant , IC 6.1 , Navigator , IC 6.1.5 , Virtuoso , Property Editor , Custom IC Design , Schematic-driven Layout , Schematic

Analog IP Verification - A Reference Guide to Practices Used

I have had a lot of discussions recently around improving the final integration of…

• 1 min read
AMS , Analog Design Environment , mixed-signal simulators , Analog Simulation , analog , IC 6.1.5 , ADE , assertion , AMS simulation , assertions , mixed signal

Will Evolving Language Standards Address Mixed-Signal Verification Problems?

Mixed-signal verification has been one of the hottest topics in the past year, and…

• 6 min read
SystemVerilog , AMS , assertion-based , SV-DC , analog , ADE , Mixed-Signal , SVA , DMS , Accellera , mixed signal , A-SVA

Virtuoso IC 5.1.41 Was Good but Virtuoso IC 6.1 is Better

With the recent release of unified custom/analog flow that is based on the latest…

• 3 min read
Analog Design Environment , Virtuoso IC6.1.5 , IC 6.1 , analog , Constraint-driven , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Custom IC Design , SKILL++ , SKILL

Is China Ready for Next Generation Mixed-signal Design?

A Chinese design engineer told me that his manager once told him: "You do not have…

• 4 min read
China , mixed-signal ToT , tech on tour , abstraction , EDA360 , analog , Mixed-Signal , Convergence , intent , japan , Silicon Realization , mixed signal , SoCs

Rapid Analog Prototyping - Handcrafted Layout Gets a Needed Productivity Boost

As more and more custom/analog designs migrate to advanced process nodes (<65nm)…

• 4 min read
AMS , parasitic-aware design , PAD , RAP , Virtuoso IC6.1.5 , custom/analog , PCells , Advanced Node , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , rapid analog prototyping , Custom IC Design , modgens , Virtuoso Layout Suite , parasitics

Early Analysis is Key – Parasitic-Aware Design

Decreasing geometries and increasing design complexity are making the task of designing…

• 3 min read
parasitic-aware design , Analog Design Environment , PAD , Virtuoso IC6.1.5 , IC 6.1.5 , ADE , Virtuoso , ADE-GXL , ADE-XL , parasitics

Virtuoso IC6.1.5: Software and Fine Red Wine

Software, like fine red wine, can get better with age as well -- but it requires…

• 7 min read
AMS , parasitic-aware design , Low Power , Virtuoso IC6.1.5 , custom/analog , Analog Simulation , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , mixed signal , Custom IC Design , DFM , parasitics

Q&A: IBM Modeling Team Describes Advanced SOI Qualification Flow In Cadence MMSIM…

Circuits implemented using sub-micron technologies require designers to meet tighter…

• 9 min read
APS , characterization , Compact Modeling Council , model qualification , IBM , MMSIM , Monte Carlo , spectreMDL , Spectre , CMC , SOI , Custom IC Design , Spice model verification , BSIMSOI

Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 2)

The design and verification methodology for analog circuits has not changed much…

• 3 min read
ABV , assertion-based , Analog Simulation , analog , SoC , Mixed-Signal , SVA , PSL , AMS simulation , assertions , mixed signal , wreal , Custom IC Design , verification

Advanced Mixed-Signal Designs Demand a Unified Methodology

Mobile, automotive, consumer and medical applications require the productive realization…

• 4 min read
conformal , RF , mixed-signal seminars , Low Power , CPF , abstraction , analog , ECOs , Mixed-Signal , Convergence , intent , Silicon Realization , mixed signal , signoff , SoCs

SKILL for the Skilled: Continued Introduction to SKILL++

In my previous posting , which provided an introduction to SKILL++, I showed a simple…

• 6 min read
Team SKILL , hierarchy , walkCvHier , IC 6.1.5 , Virtuoso , flet , Lisp , Custom IC Design , SKILL++ , SKILL

Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 1)

There is no doubt in my mind that assertions will play a significant role in analog…

• 4 min read
SystemVerilog , AMS , ABV , assertion-based , coverage , analog , Constraint-driven , Mixed-Signal , SVA , Verilog , assertion , ADE-GXL , PSL , assertions , random , MDV , Custom IC Design

SKILL for the Skilled: What is SKILL++?

The way SKILL++ deals with functions is a bit different than the way traditional…

• 5 min read
Team SKILL , hierarchy , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL , Allegro

On-Demand Webinar: Parasitic-Aware Design Part 3 -- Managing Parasitics in Back …

If you were not able to attend this recent live webinar, or were able to and would…

• less than a min read
analog , Virtuoso , Custom IC Design , parasitics

On-Demand Webinar: Parasitic-Aware Design Part 2 -- Managing Parasitics in Front…

If you were not able to attend this recent live webinar, or were able to and would…

• less than a min read
analog , Virtuoso , Custom IC Design , parasitics

On-Demand Webinar: Parasitic-Aware Design Part1 -- A Complete Analog Design Flow

If you were not able to attend this recent live webinar, or were able to and would…

• less than a min read
analog , Virtuoso , Custom IC Design , parasitics

Making Friends With Parasitic Effects

OK, so the title is perhaps a little optimistic but I'm playing off the saying …

• 2 min read
PAD , Bleasdale , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , Parasitic analysis , Custom IC Design , parasitics

SKILL for the Skilled: Rule of English Translation

An obvious criticism of my previous post SKILL for the Skilled: Making Programs…

• 3 min read
Team SKILL , English translation , Norvig , Lisp , Custom IC Design , SKILL , clarity

Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL

MDL is an immensely powerful feature in our simulators that allows designers to run…

• less than a min read

Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL

Measurement Description Language (MDL) is an immensely powerful feature in our simulators…

• less than a min read
analog , Virtuoso , spectreMDL , Spectre , MDL , Custom IC Design

SKILL for the Skilled: Making Programs Clear and Concise

The SKILL programming language augments Cadence core tool functionality for Virtuoso…

• 3 min read
Team SKILL , programming , analog , Virtuoso , Custom IC Design , SKILL , Allegro

Things You Didn't Know About Virtuoso: ADE XL--Take This Job and...Run It!

Sometimes these articles just write themselves... Last week, 3 different people asked…

• 3 min read
Analog Simulation , analog , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

Now Playing: Custom IC Videos-to-Go

I wanted to take a brief detour from my usual postings to point out a couple of new…

• 3 min read
IC 6.1 , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , IC 6.1.4 , Custom IC Design
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