Get email delivery of the Cadence blog featured here
Several weeks back, I posted my first blog on the Virtuoso® Automated Device Placement and Routing solution, highlighting the importance of analog layout automation in advanced nodes. In the subsequent blogs, I talked about automated grouping and constraint creation and automated generation of placement and routing grids, finally leading up to automated row-based placement.
Generally, in a conventional design flow on a mature node, this would be followed by routing and iterations to fix layout issues. However, at advanced nodes, we have to take care of a few additional requirements for base (device-level) layers before the layout can be routed and taken to completion. To address these requirements, the Automated Device Placement and Routing solution in Virtuoso incudes an addition step—Base Layer Fill Insertion.
Why do we need this step? How does it fit in the overall design flow?
I'll try to answer these questions in this blog.
The main reason is the need to meet the density requirements for manufacturing as well as for matching.
Device layers, such as diffusion and poly, need to meet the density goals and ensure uniformity. The automated base layer fill functionality takes care of these requirements through the addition of dummy devices, poly or other local interconnect fill, and associated cut layers in a DRC and LVS-correct manner. Adding base layer fill not only addresses density and DRC requirements, but it also takes care of matching requirements for critical analog components in the layout from a layer, device parameter, and connectivity standpoint.
We've seen that adding base layer fill is of utmost importance in advanced node device-level layouts. But it can be really tedious to add fills to your design.
With the automated device placement and routing flow, you can go through this process with just one click. The flow assistant helps you generate base layer fills through a single UI with default settings that can be overridden if needed. For example, you can choose the type of devices and parameters for the base layer fill for the entire design or for specific areas. You can also choose which layers (poly, local interconnects) are to be considered for the fill.
The automated device placement and routing solution provides a simple interface that lets you make such settings before generating the base layer fills. What you don’t have to worry about are specific values, because DRC correctness is built into this functionality. As a result, you can generate the layout quickly for resimulation and faster convergence.
Here's an animation that depicts the process.
Isn't that easy?
When I come back in two weeks, I will talk about the last and one of the most challenging tasks in the design flow, namely routing. Stay tuned and so long.
Rapid Adoption Kits
For more information on Cadence circuit design products and services, visit www.cadence.com.
Virtuosity has been our most viewed and admired blog series for a long time that has brought to fore some lesser known, yet very useful software and documentation improvements, and also shed light on some exciting new offerings in Virtuoso. We are now expanding the scope of this series by broadcasting the voice of different bloggers and experts, who would continue to preserve the legacy of Virtuosity, and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more… Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Virtuosity posts.
- Sravasti Nair