Virtuosity: Custom IC Design Flow/Methodology - Post-Layout Circuit Simulation and GDSII Generation

The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creating these IC designs by maximizing speed and silicon accuracy throughout the design process. The methodology also covers the key design domains of analog, custom digital, and RF, and supports their integration with digital standard cell blocks. 

Design Flow Stages

The figure below illustrates the five key design stages in Custom IC design methodology and the various Cadence tools one can use in each stage. In this blog, which is the fifth and the final blog in the Custom IC design Flow/Methodology series, we cover the Post-Layout Circuit Simulation and GDSII Generation design stages, which are performed after the parasitic extraction is done. We will also talk about the related Rapid Adoption Kits that are available on Cadence Learning and Support portal for you to download for free and use as a test set up to try out these and the earlier discussed design stages in the flow.

Post Layout Circuit Simulation

In the post-layout circuit simulation stage, you can verify that the analog block you designed in the first stage of the flow still meets the performance specifications when parasitics are taken into consideration. Talking of the example being used in this blog, you can run a simulation to measure the results of the adc_sample_hold block with extracted parasitics. The results will be compared with a pre-layout simulation, which will be the simulation prior to parasitic extraction, and you can verify that the analog block still meets the performance specifications when the physical effects extracted from the layout are considered.

Testbench Setup: Schematic

The maestro testbench is set up as shown and it includes the ADC clock generator and bias circuits to give a more realistic validation of the performance of the Sample and Hold (S/H) block inside the ADC. A post-layout mixed-signal simulation is first performed on the S/H block and then on the top-level Flash ADC block.

Testbench Setup: ADE Assembler Maestro View

Results Comparision: Pre and Post Layout

The ViVA XL snapshot below compares the nominal and Slow-Fast corner waveforms for pre- and post-layout simulations for the Vout_diff signal and ensures that the post-layout waveform using an av_extracted view overlaps the schematic one as expected. This helps conclude your final functional validation. 
 

Top Level Testbench Setup: Schematic

You can simulate and validate the top-level functionality and performance by using increasingly accurate circuit representations that incrementally include parasitic effects. For example, in the design scenario shown below, the schematic testbench shows the 3-bit ADC Flash design setup over which you can run a mixed-signal simulation that includes behavioral views along transistor-level designs.

Top Level Simulation Results 

Finally, you can perform a top-level mixed-signal parasitic simulation on the Flash ADC block using the black-boxed and extracted views. The Spurious Free Dynamic Range (SFDR) parameter is measured as shown below by comparing the difference between the two peaks in dBs, which for the design case below is around 7.1dB, and so it falls within the expected maximum specification limit of 19.82 dB for top-level parasitic adcflash cell-based mixed-signal simulations.

GDSII Generation

After the post-layout simulations confirm that the design meets all the specifications, the design is ready to be taped out. This is the fifth and the final stage of the IC design.

In this stage, you can generate the GDSII (Graphic Database System II) file that can then be sent to the foundry for chip fabrication. GDSII is the industry standard database format. The snapshot below shows the XStream Out form with the name of the GDSII file to be created, which is adcflash.gds for the example scenario below.

Alternatively, you can use the Open Artwork System Interchange Standard (known as OASIS). Both the methods use shapes, coordinates, and metal layers to fabricate a chip.

To try out the Custom IC Design flow, you can download a series of RAKs from the Cadence Learning and Support website. In this RAK series, each stage in the Custom IC Design Flow and Methodology is explained in detail, supported by a downloadable test database to help you try out the steps. The RAK series begins at the introduction of the design flow, followed by the schematic and layout design of the Sample and Hold ADC block, which is then followed by a pre-layout simulation setup and run. Then the RAK covers extraction of the individual blocks inside the top-level Flash ADC design, followed by a final post-layout simulation analysis to ensure the pre- and post-layout results are consistent and the specifications are met. The GDSII (Graphic Database System II) file is created as a final step, which can then be sent to the foundry for fabrication. You can run each stage in the RAK independently, or work your way through the entire flow.

For more information on Cadence Custom IC circuit design products and services, visit www.cadence.com.

Related Resources

Rapid Adoption Kits	Custom IC Design Flow/Methodology  Custom IC Design Flow/Methodology: Schematic Capture & Circuit Simulation Custom IC Design Flow/Methodology: Circuit Layout  Custom IC Design Flow/Methodology: Circuit Physical Verification and Parasitic Extraction Custom IC Design Flow/Methodology: Post Layout Circuit Simulation Custom IC Design Flow/Methodology: GDSII Generation Post-Layout Simulation Using ADE
User Guides​	Virtuoso ADE Explorer User Guide Virtuoso ADE Assembler User Guide Spectre Classic Simulator, Spectre APS, Spectre X, and Spectre XPS User Guide Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide
Blogs	Virtuosity: Custom IC Design Flow/Methodology – Introduction Virtuosity: Custom IC Design Flow/Methodology – Schematic Capture and Circuit Simulation Virtuosity: Custom IC Design Flow/Methodology – Circuit Layout Virtuosity: Custom IC Design Flow/Methodology – Circuit Physical Verification & Parasitic Extraction

Contact Us

For any questions or general feedback, please write to custom_ic_blogs@cadence.com.

Happy reading, and stay safe!

Ashish Patni, Harsh Gupta

About Virtuosity

Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of the Virtuoso environment, and a lot more. Subscribe to receive email notifications about our latest Custom IC Design blog posts.