Virtuoso Meets Maxwell: Top of the PoPs! By Exporting the Package Footprint in Virtuoso

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso® RF Solution and Virtuoso MultiTech. So, how does Virtuoso meet Maxwell? Now, Virtuoso platform supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. Watch out for our posts on Mondays.

 

I’m back again. It has been a while, but guess what? I have a lot of goodies to share with you. Since last time I posted a blog, our Virtuoso system design solutions have gone through a lot of enhancements, and more automations have been accomplished. You may already have read our blog, Virtuoso Meets Maxwell: Getting Your Existing SiP File Into Virtuoso RF Solution, which covers how you can bring your existing SiP design into the Virtuoso platform to create package technology and design libraries. The libraries include a schematic and a layout that represent your SiP layout in OpenAccess. You can bind your die footprint to the IC design to use the Edit-in-Concert capabilities and cross-fabric electromagnetic analysis between IC and package designs.

In this blog, we assume that you have already read through the Virtuoso Meets Maxwell: Getting Your Existing SiP File Into Virtuoso RF Solution and the Virtuoso Meets Maxwell: Export the Die? What Am I Exporting? To Where? blogs. Consequently, you know how the package libraries are created in Virtuoso and the requirements for exporting a die footprint.

So, you have seen how IC and package designs come together into the Virtuoso environment. Now, in this blog, we are going to take what you already learned to the next level, which means taking the package design and using it as part of a bigger system design, such as a Package-on-Package (PoP) design. I’m going to show you the initial essential steps about how to achieve that in the Virtuoso environment.

Stage 1- You have your SiP file already imported in the Virtuoso environment as well as the package technology and design libraries.

Stage 2- You need to know your package technology library and find the I/O component cell, such as BGA or LGA, to open the base cellview for review and capture the padstack’s information (in this blog, we have used a BGA):

1. In your package technology library, open the BGA base layout view.
2. Select one of the BGA balls in the layout or the Navigator assistant.
3. Click Edit – Basic – Properties.
4. Capture the cellview name of the BGA ball instance.
5. Close the layout.

Stage 3- In the Library Manager, go to the BGA Ball cellview, which is a padstack_base layout view, and follow the steps below to capture the BGA ball pin layer and change a cell property that is required for exporting the package footprint:

1. Open the padstack_base layout view.
2. Make sure all Layers are visible and selectable.
3. Click Edit – Select – Select All.
4. Click Edit – Basic – Properties.
5. Capture the pin Layer of the BGA Ball => Click OK
6. Click File – Properties.
7. Update the CellType property as pad or coverBump.
8. Close the layout.

Stage 4- Now we are going to visit our package design library, where a schematic view and a layout view get created for the top-level package design. For package footprint export to work, you need to create a schematic symbol view for the top-level design, which will be used to help for hierarchical pin mapping between this package and the next level of the design: 

1. Open the top-level package schematic design.
2. On the schematic side, pins need to be defined for each BGA ball. If these pins aren’t already created in the schematic, auto generated the pins using Module – Auto Create Pins.
3. Click Create – Cellview – From Cellview to create a schematic symbol.
4. Create symbol view from the schematic view. You can use the default pin order or make changes. 
5. Check and save the symbol view.

7. Close the schematic view, and let’s review a few requirements and recommendations for the top-level layout.
8. Open the top-level package layout design.

 

Stage 5- Now our top-level package design is ready for the package footprint export to create a package footprint library.

1. Use the following public API ,vrfExportPackage, to go through the export and library creation.

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Once the package footprint export is done successfully, you see Package export is complete in the CIW and a Package_Footprint_Lib created in your library list. You can see the views that got created are:

• abstract/base => Physical Footprint of the BGA ball map.
• layout => PCell that calls the abstract/base and adds the required parameters/properties to it.
• schematic => This is the mapping schematic that takes care of the pin name mapping for all the pins and auto-assign _EXTRA# for the duplicate/repeated pins.
• symbol =>  This is the top-level schematic symbol that can be used/instantiated in a larger system’s schematic and it gives the design a hierarchical intelligence through the mapping schematic.

To conclude, these are the stages for creating a package footprint library and using it as a part of a bigger system design, such as a PoP design. Enjoy reading!

Related Resources

Datasheet	Virtuoso RF Solution What’s New in Virtuoso
Product Manual	Virtuoso MultiTech Framework Guide Virtuoso RF Solution Guide Virtuoso Electromagnetic Solver Assistant User Guide
Free Trials	Virtuoso RF Solution - Module Layout with Edit-in-Concert Virtuoso RF Solution - EM Analysis Virtuoso RF Solution - Physical Implementation Flows

For more information on Cadence circuit design products and services, visit www.cadence.com.

Sanam Vakili

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For any questions, general feedback, or even if you want to suggest a future blog topic, write to custom_ic_blogs@cadence.com.

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching! Subscribe to receive email notifications about our latest Custom IC Design blog posts.