RTL-to-GDSII Back-End Flow: Navigating from Synthesis to Timing Signoff

Are you interested in learning the key steps to designing a physical layout from synthesis to signoff? Do you want to know the latest AI features in the RTL2GDSII back-end flow?

Join Cadence Training and Sai Srinivas P, Lead Education Application Engineer, for this free technical training webinar and get insights from industry experts:
RTL-to-GDSII Back-End Flow: Navigating from Synthesis to Timing Signoff

In this webinar, you’ll learn concepts such as logic synthesis, design-for-test logic, logic equivalence checking, implementation, and timing signoff while discovering the exciting world of back-end design flow. We’ll guide you through the essential steps in creating the final physical layout of tapeout-ready integrated circuits.

The Cadence tools we’ll use are Genus Synthesis Solution, Cadence Modus DFT Software Solution, Conformal Equivalence Checker, Innovus Implementation System, and Tempus Timing Solution.

Agenda

• Explore the synthesis to timing signoff flow
• Learn more about the Cadence tools used in each stage of the flow
• Identify the latest Cadence tool features to improve your productivity

Date and Time

Wednesday, October 29
07:00 PDT San Jose/10:00 EDT New York/15:00 GMT London/16:00 CET Berlin/17:00 IST Jerusalem/19:30 IST Bengaluru (Bangalore)/22:00 CST Beijing

To register for this webinar, sign in with your Cadence ASK – Application Support and Knowledge Portal (formerly COS)* account (email ID and password), then select Enroll. You’ll receive a confirmation email with all login details.

A Quick Reminder

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• For questions and inquiries, or issues with registration, reach out to eur_training@cadence.com.

To view our complete training offerings, visit the Cadence Training website.

Want to Dive Deep Into the Entire Flow?

Enroll in our free Cadence RTL-to-GDSII Flow training course.

*If you don’t have an ASK account, go to Cadence User Registration and complete the requested information.

There is also a Digital Badge available for the training.

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Related Courses

• Design for Test Fundamentals Training Course
• Genus Synthesis Solution with Stylus Common UI Training Course
• Innovus Block Implementation with Stylus Common UI Training Course
• Conformal Equivalence Checking Training Course
• Tempus Signoff Timing Analysis and Closure with Stylus Common UI

Training Bytes Videos

• How to Run the Synthesis Without DFT?
• RTL-to-GDSII Flow for ASIC Design Using Cadence Tools
• Demo: How to Setup the AI Assistant in the Innovus Implementation System
• Demo: How to Display Unplaced Macros in Innovus Implementation System
• Demo: Placing Pins Using Pin Editor Window in Innovus
• Demo: How to Fix Antenna Violations in Innovus Implementation System
• Demo: How to Highlight the Timing Path in Innovus Implementation System

Blogs

• Training Insights Webinar: Designing a Complete Chip Using the RTL-to-GDSII Flow
• RTLtoGDSII: Creativity meets Engineering in Chip Design
• RTL-to-GDSII Flow: I Am Not a Tool but Can Help You Implement Your Entire Design!
• Training Bytes: They May Be Shorter, But the Impact Is Stronger!

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